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openmptcprouter/root/package/boot/uboot-rockchip/patches/012-resync-rk3566-device-tree-with-mainline.patch
Ycarus (Yannick Chabanois) f2bf060a04 Update rockchip uboot
2022-11-18 18:10:38 +01:00

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From 07cb5e592c2fe682d7f176282a16f389c94f46c8 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Tue, 18 Jan 2022 19:20:40 -0500
Subject: [PATCH 12/13] resync rk3566 device tree with mainline
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/dts/rk3566-quartz64-a.dts | 285 ++++++++++++++++++++---
arch/arm/dts/rk3566.dtsi | 8 +-
arch/arm/dts/rk3568.dtsi | 29 ++-
arch/arm/dts/rk356x.dtsi | 297 ++++++++++++------------
include/dt-bindings/soc/rockchip,vop2.h | 14 ++
5 files changed, 442 insertions(+), 191 deletions(-)
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
--- a/arch/arm/dts/rk3566-quartz64-a.dts
+++ b/arch/arm/dts/rk3566-quartz64-a.dts
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
@@ -55,6 +56,17 @@
#cooling-cells = <2>;
};
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -196,7 +208,7 @@
enable-active-high;
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb20_host_en_h>;
+ pinctrl-0 = <&vcc5v0_usb20_host_en>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_usb>;
@@ -248,6 +260,29 @@
vin-supply = <&vbus>;
};
+ vcc_sys_ebc: vcc_sys_ebc {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_sys_ebc_h>;
+ regulator-boot-on;
+ regulator-name = "vcc_sys_ebc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_lcd_en: vcc_lcd_en {
+ compatible = "regulator-fixed";
+// gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc_lcd_en_h>;
+ regulator-name = "vcc_lcd_en";
+ vin-supply = <&vcc_sys>;
+ };
+
/* sourced from vcc_sys, sdio module operates internally at 3.3v */
vcc_wl: vcc_wl {
compatible = "regulator-fixed";
@@ -258,14 +293,21 @@
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_sys>;
};
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm14 0 1000000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
};
-&combphy1_usq {
+&combphy1 {
status = "okay";
rockchip,enable-ssc;
};
-&combphy2_psq {
+&combphy2 {
status = "okay";
};
@@ -302,6 +344,39 @@
};
};
+&ebc {
+ panel,width = <1872>;
+ panel,height = <1404>;
+ panel,vir_width = <1872>;
+ panel,vir_height = <1404>;
+ panel,sdck = <33300000>;
+ panel,lsl = <11>;
+ panel,lbl = <8>;
+ panel,ldl = <234>;
+ panel,lel = <23>;
+ panel,gdck-sta = <10>;
+ panel,lgonl = <215>;
+ panel,fsl = <1>;
+ panel,fbl = <4>;
+ panel,fdl = <1404>;
+ panel,fel = <12>;
+ panel,mirror = <1>;
+ panel,panel_16bit = <1>;
+ panel,panel_color = <0>;
+ panel,width-mm = <157>;
+ panel,height-mm = <210>;
+
+ io-channels = <&ebc_pmic 0>;
+ panel-supply = <&v3p3>;
+ vcom-supply = <&vcom>;
+ vdrive-supply = <&vdrive>;
+ status = "okay";
+};
+
+&eink {
+ status = "okay";
+};
+
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
@@ -325,19 +400,28 @@
status = "okay";
};
-&hdmi {
+&gpu {
+ mali-supply = <&vdd_gpu>;
status = "okay";
+};
+
+&hdmi {
avdd-0v9-supply = <&vdda_0v9>;
avdd-1v8-supply = <&vcc_1v8>;
+ status = "okay";
};
-&hdmi_in_vp0 {
- status = "okay";
+&hdmi_in {
+ hdmi_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
};
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
};
&i2c0 {
@@ -357,6 +441,7 @@
regulator-state-mem {
regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
};
};
@@ -420,8 +505,6 @@
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
@@ -571,6 +654,55 @@
};
};
+&i2c1 {
+ status = "okay";
+
+ ebc_pmic: pmic@68 {
+ compatible = "ti,tps65185";
+ reg = <0x68>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #io-channel-cells = <1>;
+ pinctrl-0 = <&ebc_pmic_pins>;
+ pinctrl-names = "default";
+ powerup-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pwr_good-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
+ vcom_ctrl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vcc_sys_ebc>;
+ vin3p3-supply = <&vcc_sys_ebc>;
+ wakeup-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
+ ti,up-sequence = <1>, <0>, <2>, <3>;
+ ti,up-delay-ms = <3>, <3>, <3>, <3>;
+ ti,down-sequence = <2>, <3>, <1>, <0>;
+ ti,down-delay-ms = <3>, <6>, <6>, <6>;
+
+ regulators {
+ v3p3: v3p3 {
+ regulator-name = "v3p3";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcom: vcom {
+ regulator-name = "vcom";
+ regulator-min-microvolt = <1450000>;
+ regulator-max-microvolt = <1450000>;
+ };
+
+ vdrive: vdrive {
+ regulator-name = "vdrive";
+ regulator-min-microvolt = <15000000>;
+ regulator-max-microvolt = <15000000>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
&i2s1_8ch {
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_sclktx
@@ -611,6 +743,21 @@
};
};
+ ebc_pmic {
+ ebc_pmic_pins: ebc-pmic-pins {
+ rockchip,pins = /* wakeup */
+ <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,
+ /* int */
+ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* pwr_good */
+ <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
+ /* pwrup */
+ <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
+ /* vcom_ctrl */
+ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
fan {
fan_en_h: fan-en-h {
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -654,7 +801,7 @@
};
usb2 {
- vcc5v0_usb20_host_en_h: vcc5v0-usb20-host-en_h {
+ vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -664,6 +811,18 @@
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ vcc_sys_ebc {
+ vcc_sys_ebc_h: vcc-sys-ebc-h {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ vcc_lcd_en {
+ vcc_lcd_en_h: vcc-lcd-en-h {
+ rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&pmu_io_domains {
@@ -681,12 +840,15 @@
/* sata1 is muxed with the usb3 port */
&sata1 {
- status = "okay";
+ status = "disabled";
+// status = "okay";
};
/* sata2 is muxed with the pcie2 slot*/
&sata2 {
+ target-supply = <&vcc3v3_pcie_p>;
status = "disabled";
+// status = "okay";
};
&sdhci {
@@ -783,6 +945,10 @@
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
&u2phy0_host {
phy-supply = <&vcc5v0_usb20_host>;
status = "okay";
@@ -793,25 +959,17 @@
status = "okay";
};
-&u2phy1_host {
- phy-supply = <&vcc5v0_usb20_host>;
+&u2phy1 {
status = "okay";
};
-&u2phy1_otg {
+&u2phy1_host {
phy-supply = <&vcc5v0_usb20_host>;
status = "okay";
};
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usbdrd_dwc3 {
+&u2phy1_otg {
+ phy-supply = <&vcc5v0_usb20_host>;
status = "okay";
};
@@ -820,13 +978,9 @@
};
/* usb3 controller is muxed with sata1 */
-&usbhost_dwc3 {
- status = "disabled";
-};
-
-/* usb3 controller is muxed with sata1 */
&usbhost30 {
- status = "disabled";
+// status = "disabled";
+ status = "okay";
};
&usb_host0_ehci {
@@ -846,15 +1000,80 @@
};
&vop {
- status = "okay";
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
};
&vop_mmu {
status = "okay";
};
-&vp0_out_hdmi {
+&vp0 {
+ vp0_out_hdmi: endpoint@RK3568_VOP2_EP_HDMI {
+ reg = <RK3568_VOP2_EP_HDMI>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
+/*
+&video_phy0 {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+ clock-master;
+
+ mipi_panel: panel@0 {
+ compatible = "feiyang,fy07024di26a30d";
+ reg = <0>;
+ backlight = <&backlight>;
+ reset-gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
+ width-mm = <154>;
+ height-mm = <86>;
+ rotation = <0>;
+// avdd-supply = <&avdd>;
+// dvdd-supply = <&vcc3v3_s0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+ };
+};
+
+&dsi0_in {
+ dsi0_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_dsi0>;
+ };
+};
+
+&dsi0_out {
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+
+};
+
+&vp1 {
+ vp1_out_dsi0: endpoint@RK3568_VOP2_EP_MIPI0 {
+ reg = <RK3568_VOP2_EP_MIPI0>;
+ remote-endpoint = <&dsi0_in_vp1>;
+ };
+};
+
+&pwm14 {
status = "okay";
+ pinctrl-0 = <&pwm14m1_pins>;
+ pinctrl-names = "default";
};
+*/
--- a/arch/arm/dts/rk3566.dtsi
+++ b/arch/arm/dts/rk3566.dtsi
@@ -23,10 +23,14 @@
};
};
-&usbdrd_dwc3 {
+&usbdrd30 {
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
- extcon = <&usb2phy0>;
+ extcon = <&u2phy0>;
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
};
+
+&vop {
+ compatible = "rockchip,rk3566-vop";
+};
--- a/arch/arm/dts/rk3568.dtsi
+++ b/arch/arm/dts/rk3568.dtsi
@@ -16,13 +16,18 @@
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
- phys = <&combphy0_us PHY_TYPE_SATA>;
+ phys = <&combphy0 PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
status = "disabled";
};
+ pipe_phy_grf0: syscon@fdc70000 {
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+ reg = <0x0 0xfdc70000 0x0 0x1000>;
+ };
+
qos_pcie3x1: qos@fe190080 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190080 0x0 0x20>;
@@ -87,19 +92,19 @@
};
};
- combphy0_us: phy@fe820000 {
+ combphy0: phy@fe820000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe820000 0x0 0x100>;
- #phy-cells = <1>;
- assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
- assigned-clock-rates = <100000000>;
- clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
+ clocks = <&pmucru CLK_PCIEPHY0_REF>,
+ <&cru PCLK_PIPEPHY0>,
<&cru PCLK_PIPE>;
clock-names = "ref", "apb", "pipe";
- resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
- reset-names = "combphy-apb", "combphy";
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY0>;
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ #phy-cells = <1>;
status = "disabled";
};
};
@@ -131,7 +136,11 @@
};
};
-&usbdrd_dwc3 {
- phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
+&usbdrd30 {
+ phys = <&u2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
};
+
+&vop {
+ compatible = "rockchip,rk3568-vop";
+};
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -159,6 +159,11 @@
};
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
@@ -234,7 +239,7 @@
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
- phys = <&combphy1_usq PHY_TYPE_SATA>;
+ phys = <&combphy1 PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
@@ -249,7 +254,7 @@
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
- phys = <&combphy2_psq PHY_TYPE_SATA>;
+ phys = <&combphy2 PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
@@ -258,66 +263,46 @@
usbdrd30: usbdrd {
compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
+ reg = <0x0 0xfcc00000 0x0 0x400000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
<&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "pipe_clk";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ dr_mode = "host";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3568_PD_PIPE>;
+ resets = <&cru SRST_USB3OTG0>;
+ reset-names = "usb3-otg";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,xhci-trb-ent-quirk;
status = "disabled";
-
- usbdrd_dwc3: dwc3@fcc00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfcc00000 0x0 0x400000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- power-domains = <&power RK3568_PD_PIPE>;
- resets = <&cru SRST_USB3OTG0>;
- reset-names = "usb3-otg";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,xhci-trb-ent-quirk;
- status = "disabled";
- };
};
usbhost30: usbhost {
compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
+ reg = <0x0 0xfd000000 0x0 0x400000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
<&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "pipe_clk";
- #address-cells = <2>;
- #size-cells = <2>;
- assigned-clocks = <&cru CLK_PCIEPHY1_REF>;
- assigned-clock-rates = <25000000>;
- ranges;
- status = "disabled";
-
- usbhost_dwc3: dwc3@fd000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xfd000000 0x0 0x400000>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
- phy-names = "usb2-phy", "usb3-phy";
- phy_type = "utmi_wide";
- power-domains = <&power RK3568_PD_PIPE>;
- resets = <&cru SRST_USB3OTG1>;
- reset-names = "usb3-host";
- snps,dis_enblslpm_quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis_u2_susphy_quirk;
- snps,dis-del-phy-power-chg-quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- status = "disabled";
- };
+ dr_mode = "host";
+ phys = <&u2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3568_PD_PIPE>;
+ resets = <&cru SRST_USB3OTG1>;
+ reset-names = "usb3-host";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
};
gic: interrupt-controller@fd400000 {
@@ -339,7 +324,7 @@
clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
<&cru PCLK_USB>;
phys = <&u2phy1_otg>;
- phy-names = "usb2-phy";
+ phy-names = "usb";
status = "disabled";
};
@@ -350,7 +335,7 @@
clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
<&cru PCLK_USB>;
phys = <&u2phy1_otg>;
- phy-names = "usb2-phy";
+ phy-names = "usb";
status = "disabled";
};
@@ -361,7 +346,7 @@
clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
<&cru PCLK_USB>;
phys = <&u2phy1_host>;
- phy-names = "usb2-phy";
+ phy-names = "usb";
status = "disabled";
};
@@ -372,7 +357,7 @@
clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
<&cru PCLK_USB>;
phys = <&u2phy1_host>;
- phy-names = "usb2-phy";
+ phy-names = "usb";
status = "disabled";
};
@@ -395,21 +380,17 @@
reg = <0x0 0xfdc60000 0x0 0x10000>;
};
- pipe_phy_grf0: syscon@fdc70000 {
- compatible = "rockchip,pipe-phy-grf", "syscon";
- reg = <0x0 0xfdc70000 0x0 0x1000>;
- };
-
pipe_phy_grf1: syscon@fdc80000 {
- compatible = "rockchip,pipe-phy-grf", "syscon";
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0x0 0xfdc80000 0x0 0x1000>;
};
pipe_phy_grf2: syscon@fdc90000 {
- compatible = "rockchip,pipe-phy-grf", "syscon";
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0x0 0xfdc90000 0x0 0x1000>;
};
+
usb2phy0_grf: syscon@fdca0000 {
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
reg = <0x0 0xfdca0000 0x0 0x8000>;
@@ -604,6 +585,28 @@
status = "disabled";
};
+ ebc: ebc@fdec0000 {
+ compatible = "rockchip,rk3568-ebc-tcon";
+ reg = <0x0 0xfdec0000 0x0 0x5000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>;
+ clock-names = "hclk", "dclk";
+ pinctrl-0 = <&ebc_pins>;
+ pinctrl-names = "default";
+ power-domains = <&power RK3568_PD_RGA>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ eink: eink@fdf00000 {
+ compatible = "rockchip,rk3568-eink-tcon";
+ reg = <0x0 0xfdf00000 0x0 0x74>;
+ clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>;
+ clock-names = "pclk", "hclk";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
sdmmc2: mmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;
@@ -665,21 +668,15 @@
};
};
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- };
-
vop: vop@fe040000 {
- compatible = "rockchip,rk3568-vop";
reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
reg-names = "regs", "gamma_lut";
- rockchip,grf = <&grf>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
iommus = <&vop_mmu>;
power-domains = <&power RK3568_PD_VO>;
+ rockchip,grf = <&grf>;
status = "disabled";
vop_out: ports {
@@ -687,39 +684,21 @@
#size-cells = <0>;
vp0: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
-
- vp0_out_hdmi: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&hdmi_in_vp0>;
- status = "disabled";
- };
};
vp1: port@1 {
+ reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
- reg = <1>;
-
- vp1_out_hdmi: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&hdmi_in_vp1>;
- status = "disabled";
- };
};
vp2: port@2 {
+ reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
- reg = <2>;
-
- vp2_out_hdmi: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&hdmi_in_vp2>;
- status = "disabled";
- };
};
};
};
@@ -728,7 +707,6 @@
compatible = "rockchip,rk3568-iommu";
reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -742,14 +720,15 @@
clocks = <&cru PCLK_HDMI_HOST>,
<&cru CLK_HDMI_SFR>,
<&cru CLK_HDMI_CEC>,
+ <&pmucru CLK_HDMI_REF>,
<&cru HCLK_VOP>;
- clock-names = "iahb", "isfr", "cec", "hclk";
+ clock-names = "iahb", "isfr", "cec", "ref", "hclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
power-domains = <&power RK3568_PD_VO>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
#sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
status = "disabled";
ports {
@@ -760,24 +739,12 @@
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+ };
- hdmi_in_vp0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vp0_out_hdmi>;
- status = "disabled";
- };
-
- hdmi_in_vp1: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vp1_out_hdmi>;
- status = "disabled";
- };
-
- hdmi_in_vp2: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&vp2_out_hdmi>;
- status = "disabled";
- };
+ hdmi_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
@@ -934,7 +901,7 @@
max-link-speed = <2>;
msi-map = <0x0 &gic 0x0 0x1000>;
num-lanes = <1>;
- phys = <&combphy2_psq PHY_TYPE_PCIE>;
+ phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0000000 0x0 0x400000>,
@@ -1048,6 +1015,43 @@
status = "disabled";
};
+ i2s2_2ch: i2s@fe420000 {
+ compatible = "rockchip,rk3568-i2s-tdm";
+ reg = <0x0 0xfe420000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
+ dmas = <&dmac1 4>, <&dmac1 5>;
+ dma-names = "tx", "rx";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ pinctrl-0 = <&i2s2m0_sclktx
+ &i2s2m0_lrcktx
+ &i2s2m0_sdi
+ &i2s2m0_sdo>;
+ pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ pdm: pdm@fe440000 {
+ compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
+ reg = <0x0 0xfe440000 0x0 0x1000>;
+ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&dmac1 9>;
+ dma-names = "rx";
+ pinctrl-0 = <&pdmm0_clk
+ &pdmm0_clk1
+ &pdmm0_sdi0
+ &pdmm0_sdi1
+ &pdmm0_sdi2
+ &pdmm0_sdi3>;
+ pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
dmac0: dmac@fe530000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe530000 0x0 0x4000>;
@@ -1487,47 +1491,15 @@
status = "disabled";
};
- combphy1_usq: phy@fe830000 {
- compatible = "rockchip,rk3568-naneng-combphy";
- reg = <0x0 0xfe830000 0x0 0x100>;
- #phy-cells = <1>;
- assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
- assigned-clock-rates = <100000000>;
- clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
- <&cru PCLK_PIPE>;
- clock-names = "ref", "apb", "pipe";
- resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
- reset-names = "combphy-apb", "combphy";
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
- status = "disabled";
- };
-
- combphy2_psq: phy@fe840000 {
- compatible = "rockchip,rk3568-naneng-combphy";
- reg = <0x0 0xfe840000 0x0 0x100>;
- #phy-cells = <1>;
- assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
- assigned-clock-rates = <100000000>;
- clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
- <&cru PCLK_PIPE>;
- clock-names = "ref", "apb", "pipe";
- resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
- reset-names = "combphy-apb", "combphy";
- rockchip,pipe-grf = <&pipegrf>;
- rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
- status = "disabled";
- };
-
- usb2phy0: usb2-phy@fe8a0000 {
+ u2phy0: usb2phy@fe8a0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8a0000 0x0 0x10000>;
clocks = <&pmucru CLK_USBPHY0_REF>;
clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "usb480m_phy";
+ clock-output-names = "clk_usbphy0_480m";
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
rockchip,usbgrf = <&usb2phy0_grf>;
+ #clock-cells = <0>;
status = "disabled";
u2phy0_host: host-port {
@@ -1541,14 +1513,15 @@
};
};
- usb2phy1: usb2-phy@fe8b0000 {
+ u2phy1: usb2phy@fe8b0000 {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8b0000 0x0 0x10000>;
clocks = <&pmucru CLK_USBPHY1_REF>;
clock-names = "phyclk";
- #clock-cells = <0>;
+ clock-output-names = "clk_usbphy1_480m";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
rockchip,usbgrf = <&usb2phy1_grf>;
+ #clock-cells = <0>;
status = "disabled";
u2phy1_host: host-port {
@@ -1562,6 +1535,38 @@
};
};
+ combphy1: phy@fe830000 {
+ compatible = "rockchip,rk3568-naneng-combphy";
+ reg = <0x0 0xfe830000 0x0 0x100>;
+ clocks = <&pmucru CLK_PCIEPHY1_REF>,
+ <&cru PCLK_PIPEPHY1>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY1>;
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ combphy2: phy@fe840000 {
+ compatible = "rockchip,rk3568-naneng-combphy";
+ reg = <0x0 0xfe840000 0x0 0x100>;
+ clocks = <&pmucru CLK_PCIEPHY2_REF>,
+ <&cru PCLK_PIPEPHY2>,
+ <&cru PCLK_PIPE>;
+ clock-names = "ref", "apb", "pipe";
+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PIPEPHY2>;
+ rockchip,pipe-grf = <&pipegrf>;
+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
--- /dev/null
+++ b/include/dt-bindings/soc/rockchip,vop2.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
+#define __DT_BINDINGS_ROCKCHIP_VOP2_H
+
+#define RK3568_VOP2_EP_RGB 0
+#define RK3568_VOP2_EP_HDMI 1
+#define RK3568_VOP2_EP_EDP 2
+#define RK3568_VOP2_EP_MIPI0 3
+#define RK3568_VOP2_EP_LVDS0 4
+#define RK3568_VOP2_EP_MIPI1 5
+#define RK3568_VOP2_EP_LVDS1 6
+
+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
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