mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-02-15 04:42:02 +00:00
3520 lines
91 KiB
Diff
3520 lines
91 KiB
Diff
From 25624318957d560ce58be672fe2fa8537716afc7 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 19 Dec 2021 15:14:47 -0500
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Subject: [PATCH 04/11] arm: dts: sync rk3568 with linux
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm/dts/Makefile | 3 +-
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arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 24 +
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arch/arm/dts/rk3566-quartz64-a.dts | 860 +++++++++++
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arch/arm/dts/rk3566.dtsi | 32 +
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arch/arm/dts/rk3568-evb.dts | 5 +
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arch/arm/dts/rk3568-pinctrl.dtsi | 9 +
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arch/arm/dts/rk3568.dtsi | 860 ++---------
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arch/arm/dts/rk356x.dtsi | 1630 ++++++++++++++++++++
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arch/arm/mach-rockchip/rk3568/rk3568.c | 2 +-
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9 files changed, 2672 insertions(+), 753 deletions(-)
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create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts
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create mode 100644 arch/arm/dts/rk3566.dtsi
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create mode 100644 arch/arm/dts/rk356x.dtsi
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -164,7 +164,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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rk3399pro-rock-pi-n10.dtb
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dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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- rk3568-evb.dtb
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+ rk3568-evb.dtb \
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+ rk3566-quartz64-a.dtb
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dtb-$(CONFIG_ROCKCHIP_RV1108) += \
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rv1108-elgin-r1.dtb \
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--- /dev/null
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+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
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@@ -0,0 +1,24 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
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+ */
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+
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+#include "rk3568-u-boot.dtsi"
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+
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+/ {
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+ chosen {
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+ stdout-path = &uart2;
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+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
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+ };
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+};
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+
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+&sdmmc0 {
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+ u-boot,dm-spl;
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+ status = "okay";
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+};
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+
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+&uart2 {
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+ clock-frequency = <24000000>;
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+ u-boot,dm-spl;
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+ status = "okay";
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+};
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--- /dev/null
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+++ b/arch/arm/dts/rk3566-quartz64-a.dts
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@@ -0,0 +1,860 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/pinctrl/rockchip.h>
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+#include "rk3566.dtsi"
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+
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+/ {
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+ model = "Pine64 RK3566 Quartz64-A Board";
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+ compatible = "pine64,quartz64-a", "rockchip,rk3566";
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+
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+ aliases {
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+ ethernet0 = &gmac1;
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+ mmc0 = &sdmmc0;
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+ mmc1 = &sdhci;
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+ };
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+
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+ chosen: chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ battery_cell: battery-cell {
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+ compatible = "simple-battery";
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+ charge-full-design-microamp-hours = <2500000>;
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+ charge-term-current-microamp = <300000>;
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+ constant-charge-current-max-microamp = <2000000>;
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+ constant-charge-voltage-max-microvolt = <4200000>;
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+ factory-internal-resistance-micro-ohms = <180000>;
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+ voltage-max-design-microvolt = <4106000>;
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+ voltage-min-design-microvolt = <3625000>;
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+
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+ ocv-capacity-celsius = <20>;
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+ ocv-capacity-table-0 = <4106000 100>, <4071000 95>, <4018000 90>, <3975000 85>,
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+ <3946000 80>, <3908000 75>, <3877000 70>, <3853000 65>,
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+ <3834000 60>, <3816000 55>, <3802000 50>, <3788000 45>,
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+ <3774000 40>, <3760000 35>, <3748000 30>, <3735000 25>,
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+ <3718000 20>, <3697000 15>, <3685000 10>, <3625000 0>;
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+ };
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+
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+ gmac1_clkin: external-gmac1-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac1_clkin";
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+ #clock-cells = <0>;
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+ };
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+
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+ fan: gpio_fan {
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+ compatible = "gpio-fan";
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+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
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+ gpio-fan,speed-map = <0 0
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+ 4500 1>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&fan_en_h>;
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+ #cooling-cells = <2>;
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led-work {
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+ label = "work-led";
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+ default-state = "off";
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+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&work_led_enable_h>;
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+ retain-state-suspended;
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+ };
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+
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+ led-diy {
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+ label = "diy-led";
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+ default-state = "on";
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+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "heartbeat";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&diy_led_enable_h>;
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+ retain-state-suspended;
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+ };
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+ };
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+
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+ rk817-sound {
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+ compatible = "simple-audio-card";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hp_det_h>;
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,hp-det-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
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+ simple-audio-card,name = "Analog RK817";
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+ simple-audio-card,mclk-fs = <256>;
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+ simple-audio-card,widgets =
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+ "Microphone", "Mic Jack",
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+ "Headphone", "Headphones",
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+ "Speaker", "Speaker";
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+ simple-audio-card,routing =
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+ "MICL", "Mic Jack",
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+ "Headphones", "HPOL",
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+ "Headphones", "HPOR",
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+ "Speaker", "SPKO";
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&i2s1_8ch>;
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+ };
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+
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+ simple-audio-card,codec {
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+ sound-dai = <&rk817>;
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+ };
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+ };
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+
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+ spdif_dit: spdif-dit {
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+ compatible = "linux,spdif-dit";
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+ #sound-dai-cells = <0>;
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+ };
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+
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+ spdif_sound: spdif-sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,name = "SPDIF";
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&spdif>;
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+ };
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+
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+ simple-audio-card,codec {
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+ sound-dai = <&spdif_dit>;
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+ };
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+ };
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+
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+ sdio_pwrseq: sdio-pwrseq {
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+ status = "okay";
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&rk817 1>;
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+ clock-names = "ext_clock";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&wifi_enable_h>;
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+ reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
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+ post-power-on-delay-ms = <100>;
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+ power-off-delay-us = <5000000>;
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+ };
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+
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+ spdif_sound: spdif-sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,name = "SPDIF";
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&spdif>;
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+ };
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+
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+ simple-audio-card,codec {
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+ sound-dai = <&spdif_dit>;
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+ };
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+ };
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+
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+ spdif_dit: spdif-dit {
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+ compatible = "linux,spdif-dit";
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+ #sound-dai-cells = <0>;
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+ };
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+
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+ vcc12v_dcin: vcc12v_dcin {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc12v_dcin";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <12000000>;
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+ regulator-max-microvolt = <12000000>;
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+ };
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+
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+ /* vbus feeds the rk817 usb input.
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+ * With no battery attached, also feeds vcc_bat+
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+ * via ON/OFF_BAT jumper
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+ */
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+ vbus: vbus {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vbus";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&vcc12v_dcin>;
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+ };
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+
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+ vcc5v0_usb: vcc5v0_usb {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_usb";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&vcc12v_dcin>;
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+ };
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+
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+ /* all four ports are controlled by one gpio
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+ * the host ports are sourced from vcc5v0_usb
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+ * the otg port is sourced from vcc5v0_midu
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+ */
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+ vcc5v0_usb20_host: vcc5v0_usb20_host {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_usb20_host";
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+ enable-active-high;
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+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc5v0_usb20_host_en_h>;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&vcc5v0_usb>;
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+ };
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+
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+ vcc5v0_usb20_otg: vcc5v0_usb20_otg {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_usb20_otg";
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+ enable-active-high;
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+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&dcdc_boost>;
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+ };
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+
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+ vcc3v3_pcie_p: vcc3v3_pcie_p {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie_enable_h>;
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+ regulator-name = "vcc3v3_pcie_p";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc_3v3>;
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+ };
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+
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+ vcc3v3_sd: vcc3v3_sd {
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+ compatible = "regulator-fixed";
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+ enable-active-low;
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+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc_sd_h>;
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+ regulator-boot-on;
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+ regulator-name = "vcc3v3_sd";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc_3v3>;
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+ };
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+
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+ /* sourced from vbus and vcc_bat+ via rk817 sw5 */
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+ vcc_sys: vcc_sys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <4400000>;
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+ regulator-max-microvolt = <4400000>;
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+ vin-supply = <&vbus>;
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+ };
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+
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+ /* sourced from vcc_sys, sdio module operates internally at 3.3v */
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+ vcc_wl: vcc_wl {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_wl";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc_sys>;
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+ };
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+};
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+
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+&combphy1_usq {
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+ status = "okay";
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+ rockchip,enable-ssc;
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+};
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+
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+&combphy2_psq {
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+ status = "okay";
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+};
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+
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+&cpu0 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&cpu2 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&cpu3 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&cpu_thermal {
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+ trips {
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+ cpu_hot: cpu_hot {
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+ temperature = <55000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map1 {
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+ trip = <&cpu_hot>;
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+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+};
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+
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+&gmac1 {
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+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
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+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
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+ clock_in_out = "input";
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+ phy-supply = <&vcc_3v3>;
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+ phy-mode = "rgmii";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac1m0_miim
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+ &gmac1m0_tx_bus2
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+ &gmac1m0_rx_bus2
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+ &gmac1m0_rgmii_clk
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+ &gmac1m0_clkinout
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+ &gmac1m0_rgmii_bus>;
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+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
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+ snps,reset-active-low;
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+ /* Reset time is 20ms, 100ms for rtl8211f */
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+ snps,reset-delays-us = <0 20000 100000>;
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+ tx_delay = <0x30>;
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+ rx_delay = <0x10>;
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+ phy-handle = <&rgmii_phy1>;
|
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+ status = "okay";
|
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+};
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+
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+&hdmi {
|
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+ status = "okay";
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+ avdd-0v9-supply = <&vdda_0v9>;
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+ avdd-1v8-supply = <&vcc_1v8>;
|
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+};
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+
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+&hdmi_in_vp0 {
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+ status = "okay";
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+};
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+
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+&gpu {
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+ mali-supply = <&vdd_gpu>;
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+ status = "okay";
|
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ vdd_cpu: regulator@1c {
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+ compatible = "tcs,tcs4525";
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+ reg = <0x1c>;
|
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+ fcs,suspend-voltage-selector = <1>;
|
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+ regulator-name = "vdd_cpu";
|
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+ regulator-min-microvolt = <800000>;
|
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+ regulator-max-microvolt = <1150000>;
|
|
+ regulator-ramp-delay = <2300>;
|
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+ regulator-always-on;
|
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+ regulator-boot-on;
|
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+ vin-supply = <&vcc_sys>;
|
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+
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+ regulator-state-mem {
|
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+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
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+
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+ rk817: pmic@20 {
|
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+ compatible = "rockchip,rk817";
|
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+ reg = <0x20>;
|
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+ interrupt-parent = <&gpio0>;
|
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+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
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+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
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+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
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+ clock-names = "mclk";
|
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+ clocks = <&cru I2S1_MCLKOUT_TX>;
|
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+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
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+ #clock-cells = <1>;
|
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+ pinctrl-names = "default";
|
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+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
|
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+ rockchip,system-power-controller;
|
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+ #sound-dai-cells = <0>;
|
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+ wakeup-source;
|
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+
|
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+ vcc1-supply = <&vcc_sys>;
|
|
+ vcc2-supply = <&vcc_sys>;
|
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+ vcc3-supply = <&vcc_sys>;
|
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+ vcc4-supply = <&vcc_sys>;
|
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+ vcc5-supply = <&vcc_sys>;
|
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+ vcc6-supply = <&vcc_sys>;
|
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+ vcc7-supply = <&vcc_sys>;
|
|
+ vcc8-supply = <&vcc_sys>;
|
|
+ vcc9-supply = <&dcdc_boost>;
|
|
+
|
|
+ regulators {
|
|
+ vdd_logic: DCDC_REG1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-init-microvolt = <900000>;
|
|
+ regulator-ramp-delay = <6001>;
|
|
+ regulator-initial-mode = <0x2>;
|
|
+ regulator-name = "vdd_logic";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <900000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_gpu: DCDC_REG2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <500000>;
|
|
+ regulator-max-microvolt = <1350000>;
|
|
+ regulator-init-microvolt = <900000>;
|
|
+ regulator-ramp-delay = <6001>;
|
|
+ regulator-initial-mode = <0x2>;
|
|
+ regulator-name = "vdd_gpu";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_ddr: DCDC_REG3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1100000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-initial-mode = <0x2>;
|
|
+ regulator-name = "vcc_ddr";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_3v3: DCDC_REG4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-initial-mode = <0x2>;
|
|
+ regulator-name = "vcc_3v3";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcca1v8_pmu: LDO_REG1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcca1v8_pmu";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdda_0v9: LDO_REG2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ regulator-name = "vdda_0v9";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdda0v9_pmu: LDO_REG3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ regulator-name = "vdda0v9_pmu";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <900000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vccio_acodec: LDO_REG4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vccio_acodec";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vccio_sd: LDO_REG5 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vccio_sd";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc3v3_pmu: LDO_REG6 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vcc3v3_pmu";
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <3300000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_1v8: LDO_REG7 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc_1v8";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc1v8_dvp: LDO_REG8 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc1v8_dvp";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc2v8_dvp: LDO_REG9 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <2800000>;
|
|
+ regulator-max-microvolt = <2800000>;
|
|
+ regulator-name = "vcc2v8_dvp";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dcdc_boost: BOOST {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ regulator-name = "boost";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ otg_switch: OTG_SWITCH {
|
|
+ regulator-name = "otg_switch";
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rk817_battery: battery {
|
|
+ monitored-battery = <&battery_cell>;
|
|
+ rockchip,resistor-sense-micro-ohms = <10000>;
|
|
+ rockchip,sleep-enter-current-microamp = <300000>;
|
|
+ rockchip,sleep-filter-current-microamp = <100000>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2s1_8ch {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s1m0_sclktx
|
|
+ &i2s1m0_lrcktx
|
|
+ &i2s1m0_sdi0
|
|
+ &i2s1m0_sdo0>;
|
|
+ rockchip,trcm-sync-tx-only;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mdio1 {
|
|
+ rgmii_phy1: ethernet-phy@0 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <0>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pcie2x1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie_reset_h>;
|
|
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+ vpcie3v3-supply = <&vcc3v3_pcie_p>;
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ bt {
|
|
+ bt_enable_h: bt-enable-h {
|
|
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ bt_host_wake_l: bt-host-wake-l {
|
|
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
+ };
|
|
+
|
|
+ bt_wake_l: bt-wake-l {
|
|
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fan {
|
|
+ fan_en_h: fan-en-h {
|
|
+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ work_led_enable_h: work-led-enable-h {
|
|
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ diy_led_enable_h: diy-led-enable-h {
|
|
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie {
|
|
+ pcie_enable_h: pcie-enable-h {
|
|
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pcie_reset_h: pcie-reset-h {
|
|
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmic {
|
|
+ pmic_int_l: pmic-int-l {
|
|
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
+ };
|
|
+
|
|
+ hp_det_h: hp-det-h {
|
|
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sdio-pwrseq {
|
|
+ wifi_enable_h: wifi-enable-h {
|
|
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2 {
|
|
+ vcc5v0_usb20_host_en_h: vcc5v0-usb20-host-en_h {
|
|
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_sd {
|
|
+ vcc_sd_h: vcc-sd-h {
|
|
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pmu_io_domains {
|
|
+ status = "okay";
|
|
+ pmuio1-supply = <&vcc3v3_pmu>;
|
|
+ pmuio2-supply = <&vcc3v3_pmu>;
|
|
+ vccio1-supply = <&vccio_acodec>;
|
|
+ vccio2-supply = <&vcc_1v8>;
|
|
+ vccio3-supply = <&vccio_sd>;
|
|
+ vccio4-supply = <&vcc_1v8>;
|
|
+ vccio5-supply = <&vcc_3v3>;
|
|
+ vccio6-supply = <&vcc1v8_dvp>;
|
|
+ vccio7-supply = <&vcc_3v3>;
|
|
+};
|
|
+
|
|
+/* sata1 is muxed with the usb3 port */
|
|
+&sata1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+/* sata2 is muxed with the pcie2 slot*/
|
|
+&sata2 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&sdhci {
|
|
+ bus-width = <8>;
|
|
+ mmc-hs200-1_8v;
|
|
+ non-removable;
|
|
+ vmmc-supply = <&vcc_3v3>;
|
|
+ vqmmc-supply = <&vcc_1v8>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc0 {
|
|
+ bus-width = <4>;
|
|
+ cap-sd-highspeed;
|
|
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
|
+ disable-wp;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
|
+ sd-uhs-sdr104;
|
|
+ vmmc-supply = <&vcc3v3_sd>;
|
|
+ vqmmc-supply = <&vccio_sd>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&spdif {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc1 {
|
|
+ bus-width = <4>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-sdio-irq;
|
|
+ disable-wp;
|
|
+ keep-power-in-suspend;
|
|
+ mmc-pwrseq = <&sdio_pwrseq>;
|
|
+ non-removable;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
|
|
+ sd-uhs-sdr104;
|
|
+ vmmc-supply = <&vcc_wl>;
|
|
+ vqmmc-supply = <&vcc_1v8>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sfc {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ flash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <108000000>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-tx-bus-width = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&tsadc {
|
|
+ /* tshut mode 0:CRU 1:GPIO */
|
|
+ rockchip,hw-tshut-mode = <1>;
|
|
+ /* tshut polarity 0:LOW 1:HIGH */
|
|
+ rockchip,hw-tshut-polarity = <0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart0_xfer>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
|
|
+ status = "okay";
|
|
+ uart-has-rtscts;
|
|
+
|
|
+ bluetooth {
|
|
+ compatible = "brcm,bcm43438-bt";
|
|
+ clocks = <&rk817 1>;
|
|
+ clock-names = "lpo";
|
|
+ device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
|
+ host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
|
|
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
|
|
+ vbat-supply = <&vcc_sys>;
|
|
+ vddio-supply = <&vcca1v8_pmu>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy0_host {
|
|
+ phy-supply = <&vcc5v0_usb20_host>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy0_otg {
|
|
+ phy-supply = <&vcc5v0_usb20_otg>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy1_host {
|
|
+ phy-supply = <&vcc5v0_usb20_host>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy1_otg {
|
|
+ phy-supply = <&vcc5v0_usb20_host>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb2phy0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb2phy1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdrd30 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+/* usb3 controller is muxed with sata1 */
|
|
+&usbhost_dwc3 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+/* usb3 controller is muxed with sata1 */
|
|
+&usbhost30 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&usb_host0_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_ohci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host1_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host1_ohci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop {
|
|
+ status = "okay";
|
|
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
|
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
|
+};
|
|
+
|
|
+&vop_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vp0_out_hdmi {
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/rk3566.dtsi
|
|
@@ -0,0 +1,32 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+
|
|
+#include "rk356x.dtsi"
|
|
+
|
|
+/ {
|
|
+ compatible = "rockchip,rk3566";
|
|
+};
|
|
+
|
|
+&pipegrf {
|
|
+ compatible = "rockchip,rk3566-pipegrf", "syscon";
|
|
+};
|
|
+
|
|
+&power {
|
|
+ power-domain@RK3568_PD_PIPE {
|
|
+ reg = <RK3568_PD_PIPE>;
|
|
+ clocks = <&cru PCLK_PIPE>;
|
|
+ pm_qos = <&qos_pcie2x1>,
|
|
+ <&qos_sata1>,
|
|
+ <&qos_sata2>,
|
|
+ <&qos_usb3_0>,
|
|
+ <&qos_usb3_1>;
|
|
+ #power-domain-cells = <0>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&usbdrd_dwc3 {
|
|
+ phys = <&u2phy0_otg>;
|
|
+ phy-names = "usb2-phy";
|
|
+ extcon = <&usb2phy0>;
|
|
+ maximum-speed = "high-speed";
|
|
+ snps,dis_u2_susphy_quirk;
|
|
+};
|
|
--- a/arch/arm/dts/rk3568-evb.dts
|
|
+++ b/arch/arm/dts/rk3568-evb.dts
|
|
@@ -74,6 +74,11 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+&sdmmc0 {
|
|
+ status = "okay";
|
|
+ max-frequency = <52000000>;
|
|
+};
|
|
+
|
|
&uart2 {
|
|
status = "okay";
|
|
};
|
|
--- a/arch/arm/dts/rk3568-pinctrl.dtsi
|
|
+++ b/arch/arm/dts/rk3568-pinctrl.dtsi
|
|
@@ -3108,4 +3108,13 @@
|
|
<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
|
|
};
|
|
};
|
|
+
|
|
+ tsadc {
|
|
+ /omit-if-no-ref/
|
|
+ tsadc_pin: tsadc-pin {
|
|
+ rockchip,pins =
|
|
+ /* tsadc_pin */
|
|
+ <0 RK_PA1 0 &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
};
|
|
--- a/arch/arm/dts/rk3568.dtsi
|
|
+++ b/arch/arm/dts/rk3568.dtsi
|
|
@@ -3,777 +3,135 @@
|
|
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
*/
|
|
|
|
-#include <dt-bindings/clock/rk3568-cru.h>
|
|
-#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
-#include <dt-bindings/interrupt-controller/irq.h>
|
|
-#include <dt-bindings/phy/phy.h>
|
|
-#include <dt-bindings/pinctrl/rockchip.h>
|
|
-#include <dt-bindings/soc/rockchip,boot-mode.h>
|
|
-#include <dt-bindings/thermal/thermal.h>
|
|
+#include "rk356x.dtsi"
|
|
|
|
/ {
|
|
compatible = "rockchip,rk3568";
|
|
|
|
- interrupt-parent = <&gic>;
|
|
- #address-cells = <2>;
|
|
- #size-cells = <2>;
|
|
-
|
|
- aliases {
|
|
- gpio0 = &gpio0;
|
|
- gpio1 = &gpio1;
|
|
- gpio2 = &gpio2;
|
|
- gpio3 = &gpio3;
|
|
- gpio4 = &gpio4;
|
|
- i2c0 = &i2c0;
|
|
- i2c1 = &i2c1;
|
|
- i2c2 = &i2c2;
|
|
- i2c3 = &i2c3;
|
|
- i2c4 = &i2c4;
|
|
- i2c5 = &i2c5;
|
|
- serial0 = &uart0;
|
|
- serial1 = &uart1;
|
|
- serial2 = &uart2;
|
|
- serial3 = &uart3;
|
|
- serial4 = &uart4;
|
|
- serial5 = &uart5;
|
|
- serial6 = &uart6;
|
|
- serial7 = &uart7;
|
|
- serial8 = &uart8;
|
|
- serial9 = &uart9;
|
|
- };
|
|
-
|
|
- cpus {
|
|
- #address-cells = <2>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- cpu0: cpu@0 {
|
|
- device_type = "cpu";
|
|
- compatible = "arm,cortex-a55";
|
|
- reg = <0x0 0x0>;
|
|
- clocks = <&scmi_clk 0>;
|
|
- enable-method = "psci";
|
|
- operating-points-v2 = <&cpu0_opp_table>;
|
|
- };
|
|
-
|
|
- cpu1: cpu@100 {
|
|
- device_type = "cpu";
|
|
- compatible = "arm,cortex-a55";
|
|
- reg = <0x0 0x100>;
|
|
- enable-method = "psci";
|
|
- operating-points-v2 = <&cpu0_opp_table>;
|
|
- };
|
|
-
|
|
- cpu2: cpu@200 {
|
|
- device_type = "cpu";
|
|
- compatible = "arm,cortex-a55";
|
|
- reg = <0x0 0x200>;
|
|
- enable-method = "psci";
|
|
- operating-points-v2 = <&cpu0_opp_table>;
|
|
- };
|
|
-
|
|
- cpu3: cpu@300 {
|
|
- device_type = "cpu";
|
|
- compatible = "arm,cortex-a55";
|
|
- reg = <0x0 0x300>;
|
|
- enable-method = "psci";
|
|
- operating-points-v2 = <&cpu0_opp_table>;
|
|
- };
|
|
+ sata0: sata@fc000000 {
|
|
+ compatible = "snps,dwc-ahci";
|
|
+ reg = <0 0xfc000000 0 0x1000>;
|
|
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
|
|
+ <&cru CLK_SATA0_RXOOB>;
|
|
+ clock-names = "sata", "pmalive", "rxoob";
|
|
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hostc";
|
|
+ phys = <&combphy0_us PHY_TYPE_SATA>;
|
|
+ phy-names = "sata-phy";
|
|
+ ports-implemented = <0x1>;
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ status = "disabled";
|
|
};
|
|
|
|
- cpu0_opp_table: cpu0-opp-table {
|
|
- compatible = "operating-points-v2";
|
|
- opp-shared;
|
|
-
|
|
- opp-408000000 {
|
|
- opp-hz = /bits/ 64 <408000000>;
|
|
- opp-microvolt = <900000 900000 1150000>;
|
|
- clock-latency-ns = <40000>;
|
|
- };
|
|
-
|
|
- opp-600000000 {
|
|
- opp-hz = /bits/ 64 <600000000>;
|
|
- opp-microvolt = <900000 900000 1150000>;
|
|
- };
|
|
-
|
|
- opp-816000000 {
|
|
- opp-hz = /bits/ 64 <816000000>;
|
|
- opp-microvolt = <900000 900000 1150000>;
|
|
- opp-suspend;
|
|
- };
|
|
-
|
|
- opp-1104000000 {
|
|
- opp-hz = /bits/ 64 <1104000000>;
|
|
- opp-microvolt = <900000 900000 1150000>;
|
|
- };
|
|
-
|
|
- opp-1416000000 {
|
|
- opp-hz = /bits/ 64 <1416000000>;
|
|
- opp-microvolt = <900000 900000 1150000>;
|
|
- };
|
|
-
|
|
- opp-1608000000 {
|
|
- opp-hz = /bits/ 64 <1608000000>;
|
|
- opp-microvolt = <975000 975000 1150000>;
|
|
- };
|
|
+ qos_pcie3x1: qos@fe190080 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe190080 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_pcie3x2: qos@fe190100 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe190100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_sata0: qos@fe190200 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe190200 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ gmac0: ethernet@fe2a0000 {
|
|
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
|
+ reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq", "eth_wake_irq";
|
|
+ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
|
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
|
+ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
|
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
|
+ <&cru PCLK_XPCS>;
|
|
+ clock-names = "stmmaceth", "mac_clk_rx",
|
|
+ "mac_clk_tx", "clk_mac_refout",
|
|
+ "aclk_mac", "pclk_mac",
|
|
+ "clk_mac_speed", "ptp_ref",
|
|
+ "pclk_xpcs";
|
|
+ resets = <&cru SRST_A_GMAC0>;
|
|
+ reset-names = "stmmaceth";
|
|
+ rockchip,grf = <&grf>;
|
|
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
|
+ snps,mixed-burst;
|
|
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
|
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
|
+ snps,tso;
|
|
+ status = "disabled";
|
|
|
|
- opp-1800000000 {
|
|
- opp-hz = /bits/ 64 <1800000000>;
|
|
- opp-microvolt = <1050000 1050000 1150000>;
|
|
+ mdio0: mdio {
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ #address-cells = <0x1>;
|
|
+ #size-cells = <0x0>;
|
|
};
|
|
|
|
- opp-1992000000 {
|
|
- opp-hz = /bits/ 64 <1992000000>;
|
|
- opp-microvolt = <1150000 1150000 1150000>;
|
|
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
+ snps,rd_osr_lmt = <8>;
|
|
+ snps,wr_osr_lmt = <4>;
|
|
};
|
|
- };
|
|
|
|
- firmware {
|
|
- scmi: scmi {
|
|
- compatible = "arm,scmi-smc";
|
|
- arm,smc-id = <0x82000010>;
|
|
- shmem = <&scmi_shmem>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
-
|
|
- scmi_clk: protocol@14 {
|
|
- reg = <0x14>;
|
|
- #clock-cells = <1>;
|
|
- };
|
|
+ gmac0_mtl_rx_setup: rx-queues-config {
|
|
+ snps,rx-queues-to-use = <1>;
|
|
+ queue0 {};
|
|
};
|
|
|
|
- };
|
|
-
|
|
- pmu {
|
|
- compatible = "arm,cortex-a55-pmu";
|
|
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
- };
|
|
-
|
|
- psci {
|
|
- compatible = "arm,psci-1.0";
|
|
- method = "smc";
|
|
- };
|
|
-
|
|
- timer {
|
|
- compatible = "arm,armv8-timer";
|
|
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
- arm,no-tick-in-suspend;
|
|
- };
|
|
-
|
|
- xin24m: xin24m {
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <24000000>;
|
|
- clock-output-names = "xin24m";
|
|
- #clock-cells = <0>;
|
|
- };
|
|
-
|
|
- xin32k: xin32k {
|
|
- compatible = "fixed-clock";
|
|
- clock-frequency = <32768>;
|
|
- clock-output-names = "xin32k";
|
|
- pinctrl-0 = <&clk32k_out0>;
|
|
- pinctrl-names = "default";
|
|
- #clock-cells = <0>;
|
|
- };
|
|
-
|
|
- sram@10f000 {
|
|
- compatible = "mmio-sram";
|
|
- reg = <0x0 0x0010f000 0x0 0x100>;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- ranges = <0 0x0 0x0010f000 0x100>;
|
|
-
|
|
- scmi_shmem: sram@0 {
|
|
- compatible = "arm,scmi-shmem";
|
|
- reg = <0x0 0x100>;
|
|
+ gmac0_mtl_tx_setup: tx-queues-config {
|
|
+ snps,tx-queues-to-use = <1>;
|
|
+ queue0 {};
|
|
};
|
|
};
|
|
|
|
- gic: interrupt-controller@fd400000 {
|
|
- compatible = "arm,gic-v3";
|
|
- reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
|
- <0x0 0xfd460000 0 0x80000>; /* GICR */
|
|
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <3>;
|
|
- mbi-alias = <0x0 0xfd100000>;
|
|
- mbi-ranges = <296 24>;
|
|
- msi-controller;
|
|
- };
|
|
-
|
|
- pmugrf: syscon@fdc20000 {
|
|
- compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
|
- reg = <0x0 0xfdc20000 0x0 0x10000>;
|
|
- };
|
|
-
|
|
- grf: syscon@fdc60000 {
|
|
- compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
|
|
- reg = <0x0 0xfdc60000 0x0 0x10000>;
|
|
- };
|
|
-
|
|
- pmucru: clock-controller@fdd00000 {
|
|
- compatible = "rockchip,rk3568-pmucru";
|
|
- reg = <0x0 0xfdd00000 0x0 0x1000>;
|
|
- #clock-cells = <1>;
|
|
- #reset-cells = <1>;
|
|
- };
|
|
-
|
|
- cru: clock-controller@fdd20000 {
|
|
- compatible = "rockchip,rk3568-cru";
|
|
- reg = <0x0 0xfdd20000 0x0 0x1000>;
|
|
- #clock-cells = <1>;
|
|
- #reset-cells = <1>;
|
|
- };
|
|
-
|
|
- i2c0: i2c@fdd40000 {
|
|
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
- reg = <0x0 0xfdd40000 0x0 0x1000>;
|
|
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
|
|
- clock-names = "i2c", "pclk";
|
|
- pinctrl-0 = <&i2c0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart0: serial@fdd50000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfdd50000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 0>, <&dmac0 1>;
|
|
- pinctrl-0 = <&uart0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm0: pwm@fdd70000 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfdd70000 0x0 0x10>;
|
|
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm0m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm1: pwm@fdd70010 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfdd70010 0x0 0x10>;
|
|
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm1m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm2: pwm@fdd70020 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfdd70020 0x0 0x10>;
|
|
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm2m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm3: pwm@fdd70030 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfdd70030 0x0 0x10>;
|
|
- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm3_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sdmmc2: mmc@fe000000 {
|
|
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
- reg = <0x0 0xfe000000 0x0 0x4000>;
|
|
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
|
|
- <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
|
|
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
- fifo-depth = <0x100>;
|
|
- max-frequency = <150000000>;
|
|
- resets = <&cru SRST_SDMMC2>;
|
|
- reset-names = "reset";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sdmmc0: mmc@fe2b0000 {
|
|
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
- reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
|
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
|
|
- <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
|
|
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
- fifo-depth = <0x100>;
|
|
- max-frequency = <150000000>;
|
|
- resets = <&cru SRST_SDMMC0>;
|
|
- reset-names = "reset";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sdmmc1: mmc@fe2c0000 {
|
|
- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
- reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
|
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
|
|
- <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
|
|
- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
- fifo-depth = <0x100>;
|
|
- max-frequency = <150000000>;
|
|
- resets = <&cru SRST_SDMMC1>;
|
|
- reset-names = "reset";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- sdhci: mmc@fe310000 {
|
|
- compatible = "rockchip,rk3568-dwcmshc";
|
|
- reg = <0x0 0xfe310000 0x0 0x10000>;
|
|
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
- assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
|
|
- assigned-clock-rates = <200000000>, <24000000>;
|
|
- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
|
- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
|
- <&cru TCLK_EMMC>;
|
|
- clock-names = "core", "bus", "axi", "block", "timer";
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- dmac0: dmac@fe530000 {
|
|
- compatible = "arm,pl330", "arm,primecell";
|
|
- reg = <0x0 0xfe530000 0x0 0x4000>;
|
|
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
- arm,pl330-periph-burst;
|
|
- clocks = <&cru ACLK_BUS>;
|
|
- clock-names = "apb_pclk";
|
|
- #dma-cells = <1>;
|
|
- };
|
|
-
|
|
- dmac1: dmac@fe550000 {
|
|
- compatible = "arm,pl330", "arm,primecell";
|
|
- reg = <0x0 0xfe550000 0x0 0x4000>;
|
|
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
- arm,pl330-periph-burst;
|
|
- clocks = <&cru ACLK_BUS>;
|
|
- clock-names = "apb_pclk";
|
|
- #dma-cells = <1>;
|
|
- };
|
|
-
|
|
- i2c1: i2c@fe5a0000 {
|
|
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
- reg = <0x0 0xfe5a0000 0x0 0x1000>;
|
|
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
|
- clock-names = "i2c", "pclk";
|
|
- pinctrl-0 = <&i2c1_xfer>;
|
|
- pinctrl-names = "default";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c2: i2c@fe5b0000 {
|
|
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
- reg = <0x0 0xfe5b0000 0x0 0x1000>;
|
|
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
|
- clock-names = "i2c", "pclk";
|
|
- pinctrl-0 = <&i2c2m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c3: i2c@fe5c0000 {
|
|
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
- reg = <0x0 0xfe5c0000 0x0 0x1000>;
|
|
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
|
- clock-names = "i2c", "pclk";
|
|
- pinctrl-0 = <&i2c3m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c4: i2c@fe5d0000 {
|
|
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
- reg = <0x0 0xfe5d0000 0x0 0x1000>;
|
|
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
|
- clock-names = "i2c", "pclk";
|
|
- pinctrl-0 = <&i2c4m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- i2c5: i2c@fe5e0000 {
|
|
- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
- reg = <0x0 0xfe5e0000 0x0 0x1000>;
|
|
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
|
- clock-names = "i2c", "pclk";
|
|
- pinctrl-0 = <&i2c5m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- wdt: watchdog@fe600000 {
|
|
- compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
|
|
- reg = <0x0 0xfe600000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
|
- clock-names = "tclk", "pclk";
|
|
- };
|
|
-
|
|
- uart1: serial@fe650000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe650000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 2>, <&dmac0 3>;
|
|
- pinctrl-0 = <&uart1m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart2: serial@fe660000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe660000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 4>, <&dmac0 5>;
|
|
- pinctrl-0 = <&uart2m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart3: serial@fe670000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe670000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 6>, <&dmac0 7>;
|
|
- pinctrl-0 = <&uart3m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart4: serial@fe680000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe680000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 8>, <&dmac0 9>;
|
|
- pinctrl-0 = <&uart4m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart5: serial@fe690000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe690000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 10>, <&dmac0 11>;
|
|
- pinctrl-0 = <&uart5m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart6: serial@fe6a0000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe6a0000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 12>, <&dmac0 13>;
|
|
- pinctrl-0 = <&uart6m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart7: serial@fe6b0000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe6b0000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 14>, <&dmac0 15>;
|
|
- pinctrl-0 = <&uart7m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart8: serial@fe6c0000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe6c0000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 16>, <&dmac0 17>;
|
|
- pinctrl-0 = <&uart8m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- uart9: serial@fe6d0000 {
|
|
- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
- reg = <0x0 0xfe6d0000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
|
- clock-names = "baudclk", "apb_pclk";
|
|
- dmas = <&dmac0 18>, <&dmac0 19>;
|
|
- pinctrl-0 = <&uart9m0_xfer>;
|
|
- pinctrl-names = "default";
|
|
- reg-io-width = <4>;
|
|
- reg-shift = <2>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm4: pwm@fe6e0000 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe6e0000 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm4_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm5: pwm@fe6e0010 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe6e0010 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm5_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm6: pwm@fe6e0020 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe6e0020 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm6_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm7: pwm@fe6e0030 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe6e0030 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm7_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm8: pwm@fe6f0000 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe6f0000 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm8m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm9: pwm@fe6f0010 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe6f0010 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm9m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm10: pwm@fe6f0020 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe6f0020 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm10m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm11: pwm@fe6f0030 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe6f0030 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm11m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm12: pwm@fe700000 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe700000 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm12m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm13: pwm@fe700010 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe700010 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm13m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
- };
|
|
-
|
|
- pwm14: pwm@fe700020 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe700020 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm14m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
+ combphy0_us: phy@fe820000 {
|
|
+ compatible = "rockchip,rk3568-naneng-combphy";
|
|
+ reg = <0x0 0xfe820000 0x0 0x100>;
|
|
+ #phy-cells = <1>;
|
|
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
|
+ assigned-clock-rates = <100000000>;
|
|
+ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
|
|
+ <&cru PCLK_PIPE>;
|
|
+ clock-names = "ref", "apb", "pipe";
|
|
+ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
|
|
+ reset-names = "combphy-apb", "combphy";
|
|
+ rockchip,pipe-grf = <&pipegrf>;
|
|
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
|
status = "disabled";
|
|
};
|
|
+};
|
|
|
|
- pwm15: pwm@fe700030 {
|
|
- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
- reg = <0x0 0xfe700030 0x0 0x10>;
|
|
- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
- clock-names = "pwm", "pclk";
|
|
- pinctrl-0 = <&pwm15m0_pins>;
|
|
- pinctrl-names = "active";
|
|
- #pwm-cells = <3>;
|
|
- status = "disabled";
|
|
+&cpu0_opp_table {
|
|
+ opp-1992000000 {
|
|
+ opp-hz = /bits/ 64 <1992000000>;
|
|
+ opp-microvolt = <1150000 1150000 1150000>;
|
|
};
|
|
+};
|
|
|
|
- pinctrl: pinctrl {
|
|
- compatible = "rockchip,rk3568-pinctrl";
|
|
- rockchip,grf = <&grf>;
|
|
- rockchip,pmu = <&pmugrf>;
|
|
- #address-cells = <2>;
|
|
- #size-cells = <2>;
|
|
- ranges;
|
|
-
|
|
- gpio0: gpio@fdd60000 {
|
|
- compatible = "rockchip,gpio-bank";
|
|
- reg = <0x0 0xfdd60000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- };
|
|
-
|
|
- gpio1: gpio@fe740000 {
|
|
- compatible = "rockchip,gpio-bank";
|
|
- reg = <0x0 0xfe740000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- };
|
|
-
|
|
- gpio2: gpio@fe750000 {
|
|
- compatible = "rockchip,gpio-bank";
|
|
- reg = <0x0 0xfe750000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- };
|
|
-
|
|
- gpio3: gpio@fe760000 {
|
|
- compatible = "rockchip,gpio-bank";
|
|
- reg = <0x0 0xfe760000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- };
|
|
+&pipegrf {
|
|
+ compatible = "rockchip,rk3568-pipegrf", "syscon";
|
|
+};
|
|
|
|
- gpio4: gpio@fe770000 {
|
|
- compatible = "rockchip,gpio-bank";
|
|
- reg = <0x0 0xfe770000 0x0 0x100>;
|
|
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
- interrupt-controller;
|
|
- #interrupt-cells = <2>;
|
|
- };
|
|
+&power {
|
|
+ power-domain@RK3568_PD_PIPE {
|
|
+ reg = <RK3568_PD_PIPE>;
|
|
+ clocks = <&cru PCLK_PIPE>;
|
|
+ pm_qos = <&qos_pcie2x1>,
|
|
+ <&qos_pcie3x1>,
|
|
+ <&qos_pcie3x2>,
|
|
+ <&qos_sata0>,
|
|
+ <&qos_sata1>,
|
|
+ <&qos_sata2>,
|
|
+ <&qos_usb3_0>,
|
|
+ <&qos_usb3_1>;
|
|
+ #power-domain-cells = <0>;
|
|
};
|
|
};
|
|
|
|
-#include "rk3568-pinctrl.dtsi"
|
|
+&usbdrd_dwc3 {
|
|
+ phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/rk356x.dtsi
|
|
@@ -0,0 +1,1630 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/clock/rk3568-cru.h>
|
|
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
+#include <dt-bindings/interrupt-controller/irq.h>
|
|
+#include <dt-bindings/phy/phy.h>
|
|
+#include <dt-bindings/pinctrl/rockchip.h>
|
|
+#include <dt-bindings/power/rk3568-power.h>
|
|
+#include <dt-bindings/soc/rockchip,boot-mode.h>
|
|
+#include <dt-bindings/thermal/thermal.h>
|
|
+
|
|
+/ {
|
|
+ interrupt-parent = <&gic>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ aliases {
|
|
+ gpio0 = &gpio0;
|
|
+ gpio1 = &gpio1;
|
|
+ gpio2 = &gpio2;
|
|
+ gpio3 = &gpio3;
|
|
+ gpio4 = &gpio4;
|
|
+ i2c0 = &i2c0;
|
|
+ i2c1 = &i2c1;
|
|
+ i2c2 = &i2c2;
|
|
+ i2c3 = &i2c3;
|
|
+ i2c4 = &i2c4;
|
|
+ i2c5 = &i2c5;
|
|
+ serial0 = &uart0;
|
|
+ serial1 = &uart1;
|
|
+ serial2 = &uart2;
|
|
+ serial3 = &uart3;
|
|
+ serial4 = &uart4;
|
|
+ serial5 = &uart5;
|
|
+ serial6 = &uart6;
|
|
+ serial7 = &uart7;
|
|
+ serial8 = &uart8;
|
|
+ serial9 = &uart9;
|
|
+ };
|
|
+
|
|
+ cpus {
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cpu0: cpu@0 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a55";
|
|
+ reg = <0x0 0x0>;
|
|
+ clocks = <&scmi_clk 0>;
|
|
+ #cooling-cells = <2>;
|
|
+ enable-method = "psci";
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ };
|
|
+
|
|
+ cpu1: cpu@100 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a55";
|
|
+ reg = <0x0 0x100>;
|
|
+ #cooling-cells = <2>;
|
|
+ enable-method = "psci";
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ };
|
|
+
|
|
+ cpu2: cpu@200 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a55";
|
|
+ reg = <0x0 0x200>;
|
|
+ #cooling-cells = <2>;
|
|
+ enable-method = "psci";
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ };
|
|
+
|
|
+ cpu3: cpu@300 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a55";
|
|
+ reg = <0x0 0x300>;
|
|
+ #cooling-cells = <2>;
|
|
+ enable-method = "psci";
|
|
+ operating-points-v2 = <&cpu0_opp_table>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cpu0_opp_table: opp-table-0 {
|
|
+ compatible = "operating-points-v2";
|
|
+ opp-shared;
|
|
+
|
|
+ opp-408000000 {
|
|
+ opp-hz = /bits/ 64 <408000000>;
|
|
+ opp-microvolt = <900000 900000 1150000>;
|
|
+ clock-latency-ns = <40000>;
|
|
+ };
|
|
+
|
|
+ opp-600000000 {
|
|
+ opp-hz = /bits/ 64 <600000000>;
|
|
+ opp-microvolt = <900000 900000 1150000>;
|
|
+ };
|
|
+
|
|
+ opp-816000000 {
|
|
+ opp-hz = /bits/ 64 <816000000>;
|
|
+ opp-microvolt = <900000 900000 1150000>;
|
|
+ opp-suspend;
|
|
+ };
|
|
+
|
|
+ opp-1104000000 {
|
|
+ opp-hz = /bits/ 64 <1104000000>;
|
|
+ opp-microvolt = <900000 900000 1150000>;
|
|
+ };
|
|
+
|
|
+ opp-1416000000 {
|
|
+ opp-hz = /bits/ 64 <1416000000>;
|
|
+ opp-microvolt = <900000 900000 1150000>;
|
|
+ };
|
|
+
|
|
+ opp-1608000000 {
|
|
+ opp-hz = /bits/ 64 <1608000000>;
|
|
+ opp-microvolt = <975000 975000 1150000>;
|
|
+ };
|
|
+
|
|
+ opp-1800000000 {
|
|
+ opp-hz = /bits/ 64 <1800000000>;
|
|
+ opp-microvolt = <1050000 1050000 1150000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gpu_opp_table: gpu-opp-table {
|
|
+ compatible = "operating-points-v2";
|
|
+
|
|
+ opp-200000000 {
|
|
+ opp-hz = /bits/ 64 <200000000>;
|
|
+ opp-microvolt = <825000>;
|
|
+ };
|
|
+
|
|
+ opp-300000000 {
|
|
+ opp-hz = /bits/ 64 <300000000>;
|
|
+ opp-microvolt = <825000>;
|
|
+ };
|
|
+
|
|
+ opp-400000000 {
|
|
+ opp-hz = /bits/ 64 <400000000>;
|
|
+ opp-microvolt = <825000>;
|
|
+ };
|
|
+
|
|
+ opp-600000000 {
|
|
+ opp-hz = /bits/ 64 <600000000>;
|
|
+ opp-microvolt = <825000>;
|
|
+ };
|
|
+
|
|
+ opp-700000000 {
|
|
+ opp-hz = /bits/ 64 <700000000>;
|
|
+ opp-microvolt = <900000>;
|
|
+ };
|
|
+
|
|
+ opp-800000000 {
|
|
+ opp-hz = /bits/ 64 <800000000>;
|
|
+ opp-microvolt = <1000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ firmware {
|
|
+ scmi: scmi {
|
|
+ compatible = "arm,scmi-smc";
|
|
+ arm,smc-id = <0x82000010>;
|
|
+ shmem = <&scmi_shmem>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ scmi_clk: protocol@14 {
|
|
+ reg = <0x14>;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmu {
|
|
+ compatible = "arm,cortex-a55-pmu";
|
|
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
|
+ };
|
|
+
|
|
+ psci {
|
|
+ compatible = "arm,psci-1.0";
|
|
+ method = "smc";
|
|
+ };
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv8-timer";
|
|
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ arm,no-tick-in-suspend;
|
|
+ };
|
|
+
|
|
+ xin24m: xin24m {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <24000000>;
|
|
+ clock-output-names = "xin24m";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
+ xin32k: xin32k {
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <32768>;
|
|
+ clock-output-names = "xin32k";
|
|
+ pinctrl-0 = <&clk32k_out0>;
|
|
+ pinctrl-names = "default";
|
|
+ #clock-cells = <0>;
|
|
+ };
|
|
+
|
|
+ sram@10f000 {
|
|
+ compatible = "mmio-sram";
|
|
+ reg = <0x0 0x0010f000 0x0 0x100>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0x0 0x0010f000 0x100>;
|
|
+
|
|
+ scmi_shmem: sram@0 {
|
|
+ compatible = "arm,scmi-shmem";
|
|
+ reg = <0x0 0x100>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sata1: sata@fc400000 {
|
|
+ compatible = "snps,dwc-ahci";
|
|
+ reg = <0 0xfc400000 0 0x1000>;
|
|
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
|
|
+ <&cru CLK_SATA1_RXOOB>;
|
|
+ clock-names = "sata", "pmalive", "rxoob";
|
|
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hostc";
|
|
+ phys = <&combphy1_usq PHY_TYPE_SATA>;
|
|
+ phy-names = "sata-phy";
|
|
+ ports-implemented = <0x1>;
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sata2: sata@fc800000 {
|
|
+ compatible = "snps,dwc-ahci";
|
|
+ reg = <0 0xfc800000 0 0x1000>;
|
|
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
|
|
+ <&cru CLK_SATA2_RXOOB>;
|
|
+ clock-names = "sata", "pmalive", "rxoob";
|
|
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hostc";
|
|
+ phys = <&combphy2_psq PHY_TYPE_SATA>;
|
|
+ phy-names = "sata-phy";
|
|
+ ports-implemented = <0x1>;
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usbdrd30: usbdrd {
|
|
+ compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
|
|
+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
|
|
+ <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>;
|
|
+ clock-names = "ref_clk", "suspend_clk",
|
|
+ "bus_clk", "pipe_clk";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ usbdrd_dwc3: dwc3@fcc00000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0xfcc00000 0x0 0x400000>;
|
|
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dr_mode = "host";
|
|
+ phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ phy_type = "utmi_wide";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ resets = <&cru SRST_USB3OTG0>;
|
|
+ reset-names = "usb3-otg";
|
|
+ snps,dis_enblslpm_quirk;
|
|
+ snps,dis-u2-freeclk-exists-quirk;
|
|
+ snps,dis-del-phy-power-chg-quirk;
|
|
+ snps,dis-tx-ipgap-linecheck-quirk;
|
|
+ snps,xhci-trb-ent-quirk;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usbhost30: usbhost {
|
|
+ compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
|
|
+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
|
|
+ <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>;
|
|
+ clock-names = "ref_clk", "suspend_clk",
|
|
+ "bus_clk", "pipe_clk";
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ assigned-clocks = <&cru CLK_PCIEPHY1_REF>;
|
|
+ assigned-clock-rates = <25000000>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ usbhost_dwc3: dwc3@fd000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0xfd000000 0x0 0x400000>;
|
|
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ dr_mode = "host";
|
|
+ phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ phy_type = "utmi_wide";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ resets = <&cru SRST_USB3OTG1>;
|
|
+ reset-names = "usb3-host";
|
|
+ snps,dis_enblslpm_quirk;
|
|
+ snps,dis-u2-freeclk-exists-quirk;
|
|
+ snps,dis_u2_susphy_quirk;
|
|
+ snps,dis-del-phy-power-chg-quirk;
|
|
+ snps,dis-tx-ipgap-linecheck-quirk;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gic: interrupt-controller@fd400000 {
|
|
+ compatible = "arm,gic-v3";
|
|
+ reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
|
+ <0x0 0xfd460000 0 0x80000>; /* GICR */
|
|
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <3>;
|
|
+ mbi-alias = <0x0 0xfd410000>;
|
|
+ mbi-ranges = <296 24>;
|
|
+ msi-controller;
|
|
+ };
|
|
+
|
|
+ usb_host0_ehci: usb@fd800000 {
|
|
+ compatible = "generic-ehci";
|
|
+ reg = <0x0 0xfd800000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
|
+ <&cru PCLK_USB>;
|
|
+ phys = <&u2phy1_otg>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host0_ohci: usb@fd840000 {
|
|
+ compatible = "generic-ohci";
|
|
+ reg = <0x0 0xfd840000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
|
+ <&cru PCLK_USB>;
|
|
+ phys = <&u2phy1_otg>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host1_ehci: usb@fd880000 {
|
|
+ compatible = "generic-ehci";
|
|
+ reg = <0x0 0xfd880000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
|
+ <&cru PCLK_USB>;
|
|
+ phys = <&u2phy1_host>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_host1_ohci: usb@fd8c0000 {
|
|
+ compatible = "generic-ohci";
|
|
+ reg = <0x0 0xfd8c0000 0x0 0x40000>;
|
|
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
|
+ <&cru PCLK_USB>;
|
|
+ phys = <&u2phy1_host>;
|
|
+ phy-names = "usb2-phy";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pmugrf: syscon@fdc20000 {
|
|
+ compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
|
+ reg = <0x0 0xfdc20000 0x0 0x10000>;
|
|
+
|
|
+ pmu_io_domains: io-domains {
|
|
+ compatible = "rockchip,rk3568-pmu-io-voltage-domain";
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pipegrf: syscon@fdc50000 {
|
|
+ reg = <0x0 0xfdc50000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ grf: syscon@fdc60000 {
|
|
+ compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
|
|
+ reg = <0x0 0xfdc60000 0x0 0x10000>;
|
|
+ };
|
|
+
|
|
+ pipe_phy_grf0: syscon@fdc70000 {
|
|
+ compatible = "rockchip,pipe-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdc70000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ pipe_phy_grf1: syscon@fdc80000 {
|
|
+ compatible = "rockchip,pipe-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdc80000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ pipe_phy_grf2: syscon@fdc90000 {
|
|
+ compatible = "rockchip,pipe-phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdc90000 0x0 0x1000>;
|
|
+ };
|
|
+
|
|
+ usb2phy0_grf: syscon@fdca0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdca0000 0x0 0x8000>;
|
|
+ };
|
|
+
|
|
+ usb2phy1_grf: syscon@fdca8000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
|
+ reg = <0x0 0xfdca8000 0x0 0x8000>;
|
|
+ };
|
|
+
|
|
+ pmucru: clock-controller@fdd00000 {
|
|
+ compatible = "rockchip,rk3568-pmucru";
|
|
+ reg = <0x0 0xfdd00000 0x0 0x1000>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ cru: clock-controller@fdd20000 {
|
|
+ compatible = "rockchip,rk3568-cru";
|
|
+ reg = <0x0 0xfdd20000 0x0 0x1000>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
|
+ assigned-clock-rates = <1200000000>, <200000000>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ };
|
|
+
|
|
+ i2c0: i2c@fdd40000 {
|
|
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfdd40000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ pinctrl-0 = <&i2c0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart0: serial@fdd50000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfdd50000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 0>, <&dmac0 1>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm0: pwm@fdd70000 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfdd70000 0x0 0x10>;
|
|
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm0m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm1: pwm@fdd70010 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfdd70010 0x0 0x10>;
|
|
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm1m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm2: pwm@fdd70020 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfdd70020 0x0 0x10>;
|
|
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm2m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm3: pwm@fdd70030 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfdd70030 0x0 0x10>;
|
|
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm3_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pmu: power-management@fdd90000 {
|
|
+ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
|
|
+ reg = <0x0 0xfdd90000 0x0 0x1000>;
|
|
+
|
|
+ power: power-controller {
|
|
+ compatible = "rockchip,rk3568-power-controller";
|
|
+ #power-domain-cells = <1>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ /* These power domains are grouped by VD_GPU */
|
|
+ power-domain@RK3568_PD_GPU {
|
|
+ reg = <RK3568_PD_GPU>;
|
|
+ clocks = <&cru ACLK_GPU_PRE>,
|
|
+ <&cru PCLK_GPU_PRE>;
|
|
+ pm_qos = <&qos_gpu>;
|
|
+ #power-domain-cells = <0>;
|
|
+ };
|
|
+
|
|
+ /* These power domains are grouped by VD_LOGIC */
|
|
+ power-domain@RK3568_PD_VI {
|
|
+ reg = <RK3568_PD_VI>;
|
|
+ clocks = <&cru HCLK_VI>,
|
|
+ <&cru PCLK_VI>;
|
|
+ pm_qos = <&qos_isp>,
|
|
+ <&qos_vicap0>,
|
|
+ <&qos_vicap1>;
|
|
+ #power-domain-cells = <0>;
|
|
+ };
|
|
+
|
|
+ power-domain@RK3568_PD_VO {
|
|
+ reg = <RK3568_PD_VO>;
|
|
+ clocks = <&cru HCLK_VO>,
|
|
+ <&cru PCLK_VO>,
|
|
+ <&cru ACLK_VOP_PRE>;
|
|
+ pm_qos = <&qos_hdcp>,
|
|
+ <&qos_vop_m0>,
|
|
+ <&qos_vop_m1>;
|
|
+ #power-domain-cells = <0>;
|
|
+ };
|
|
+
|
|
+ power-domain@RK3568_PD_RGA {
|
|
+ reg = <RK3568_PD_RGA>;
|
|
+ clocks = <&cru HCLK_RGA_PRE>,
|
|
+ <&cru PCLK_RGA_PRE>;
|
|
+ pm_qos = <&qos_ebc>,
|
|
+ <&qos_iep>,
|
|
+ <&qos_jpeg_dec>,
|
|
+ <&qos_jpeg_enc>,
|
|
+ <&qos_rga_rd>,
|
|
+ <&qos_rga_wr>;
|
|
+ #power-domain-cells = <0>;
|
|
+ };
|
|
+
|
|
+ power-domain@RK3568_PD_VPU {
|
|
+ reg = <RK3568_PD_VPU>;
|
|
+ clocks = <&cru HCLK_VPU_PRE>;
|
|
+ pm_qos = <&qos_vpu>;
|
|
+ #power-domain-cells = <0>;
|
|
+ };
|
|
+
|
|
+ power-domain@RK3568_PD_RKVDEC {
|
|
+ clocks = <&cru HCLK_RKVDEC_PRE>;
|
|
+ reg = <RK3568_PD_RKVDEC>;
|
|
+ pm_qos = <&qos_rkvdec>;
|
|
+ #power-domain-cells = <0>;
|
|
+ };
|
|
+
|
|
+ power-domain@RK3568_PD_RKVENC {
|
|
+ reg = <RK3568_PD_RKVENC>;
|
|
+ clocks = <&cru HCLK_RKVENC_PRE>;
|
|
+ pm_qos = <&qos_rkvenc_rd_m0>,
|
|
+ <&qos_rkvenc_rd_m1>,
|
|
+ <&qos_rkvenc_wr_m0>;
|
|
+ #power-domain-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gpu: gpu@fde60000 {
|
|
+ compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
|
|
+ reg = <0x0 0xfde60000 0x0 0x4000>;
|
|
+
|
|
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "job", "mmu", "gpu";
|
|
+ clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
|
|
+ clock-names = "core", "bus";
|
|
+ operating-points-v2 = <&gpu_opp_table>;
|
|
+ #cooling-cells = <2>;
|
|
+ power-domains = <&power RK3568_PD_GPU>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdmmc2: mmc@fe000000 {
|
|
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
+ reg = <0x0 0xfe000000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
|
|
+ <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
|
|
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
+ fifo-depth = <0x100>;
|
|
+ max-frequency = <150000000>;
|
|
+ resets = <&cru SRST_SDMMC2>;
|
|
+ reset-names = "reset";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gmac1: ethernet@fe010000 {
|
|
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
|
+ reg = <0x0 0xfe010000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq", "eth_wake_irq";
|
|
+ clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
|
|
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
|
|
+ <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
|
|
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
|
|
+ clock-names = "stmmaceth", "mac_clk_rx",
|
|
+ "mac_clk_tx", "clk_mac_refout",
|
|
+ "aclk_mac", "pclk_mac",
|
|
+ "clk_mac_speed", "ptp_ref";
|
|
+ resets = <&cru SRST_A_GMAC1>;
|
|
+ reset-names = "stmmaceth";
|
|
+ rockchip,grf = <&grf>;
|
|
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
|
|
+ snps,mixed-burst;
|
|
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
|
|
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
|
|
+ snps,tso;
|
|
+ status = "disabled";
|
|
+
|
|
+ mdio1: mdio {
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ #address-cells = <0x1>;
|
|
+ #size-cells = <0x0>;
|
|
+ };
|
|
+
|
|
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
+ snps,rd_osr_lmt = <8>;
|
|
+ snps,wr_osr_lmt = <4>;
|
|
+ };
|
|
+
|
|
+ gmac1_mtl_rx_setup: rx-queues-config {
|
|
+ snps,rx-queues-to-use = <1>;
|
|
+ queue0 {};
|
|
+ };
|
|
+
|
|
+ gmac1_mtl_tx_setup: tx-queues-config {
|
|
+ snps,tx-queues-to-use = <1>;
|
|
+ queue0 {};
|
|
+ };
|
|
+ };
|
|
+
|
|
+ display_subsystem: display-subsystem {
|
|
+ compatible = "rockchip,display-subsystem";
|
|
+ ports = <&vop_out>;
|
|
+ };
|
|
+
|
|
+ vop: vop@fe040000 {
|
|
+ compatible = "rockchip,rk3568-vop";
|
|
+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
|
|
+ reg-names = "regs", "gamma_lut";
|
|
+ rockchip,grf = <&grf>;
|
|
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
|
|
+ clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
|
|
+ iommus = <&vop_mmu>;
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ status = "disabled";
|
|
+
|
|
+ vop_out: ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ vp0: port@0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0>;
|
|
+
|
|
+ vp0_out_hdmi: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&hdmi_in_vp0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vp1: port@1 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <1>;
|
|
+
|
|
+ vp1_out_hdmi: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&hdmi_in_vp1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vp2: port@2 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <2>;
|
|
+
|
|
+ vp2_out_hdmi: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&hdmi_in_vp2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vop_mmu: iommu@fe043e00 {
|
|
+ compatible = "rockchip,rk3568-iommu";
|
|
+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "vop_mmu";
|
|
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
|
+ clock-names = "aclk", "iface";
|
|
+ #iommu-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ hdmi: hdmi@fe0a0000 {
|
|
+ compatible = "rockchip,rk3568-dw-hdmi";
|
|
+ reg = <0x0 0xfe0a0000 0x0 0x20000>;
|
|
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_HDMI_HOST>,
|
|
+ <&cru CLK_HDMI_SFR>,
|
|
+ <&cru CLK_HDMI_CEC>,
|
|
+ <&cru HCLK_VOP>;
|
|
+ clock-names = "iahb", "isfr", "cec", "hclk";
|
|
+ power-domains = <&power RK3568_PD_VO>;
|
|
+ reg-io-width = <4>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ hdmi_in: port@0 {
|
|
+ reg = <0>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ hdmi_in_vp0: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&vp0_out_hdmi>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ hdmi_in_vp1: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&vp1_out_hdmi>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ hdmi_in_vp2: endpoint@2 {
|
|
+ reg = <2>;
|
|
+ remote-endpoint = <&vp2_out_hdmi>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qos_gpu: qos@fe128000 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe128000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rkvenc_rd_m0: qos@fe138080 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe138080 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rkvenc_rd_m1: qos@fe138100 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe138100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rkvenc_wr_m0: qos@fe138180 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe138180 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_isp: qos@fe148000 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe148000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vicap0: qos@fe148080 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe148080 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vicap1: qos@fe148100 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe148100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vpu: qos@fe150000 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe150000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_ebc: qos@fe158000 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe158000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_iep: qos@fe158100 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe158100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_jpeg_dec: qos@fe158180 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe158180 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_jpeg_enc: qos@fe158200 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe158200 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rga_rd: qos@fe158280 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe158280 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rga_wr: qos@fe158300 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe158300 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_npu: qos@fe180000 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe180000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_pcie2x1: qos@fe190000 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe190000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_sata1: qos@fe190280 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe190280 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_sata2: qos@fe190300 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe190300 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_usb3_0: qos@fe190380 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe190380 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_usb3_1: qos@fe190400 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe190400 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_rkvdec: qos@fe198000 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe198000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_hdcp: qos@fe1a8000 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe1a8000 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vop_m0: qos@fe1a8080 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe1a8080 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ qos_vop_m1: qos@fe1a8100 {
|
|
+ compatible = "rockchip,rk3568-qos", "syscon";
|
|
+ reg = <0x0 0xfe1a8100 0x0 0x20>;
|
|
+ };
|
|
+
|
|
+ pcie2x1: pcie@fe260000 {
|
|
+ compatible = "rockchip,rk3568-pcie";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ bus-range = <0x0 0xf>;
|
|
+ assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
|
|
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
|
|
+ <&cru CLK_PCIE20_AUX_NDFT>;
|
|
+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
|
|
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
|
|
+ <&cru CLK_PCIE20_AUX_NDFT>;
|
|
+ clock-names = "aclk_mst", "aclk_slv",
|
|
+ "aclk_dbi", "pclk", "aux";
|
|
+ device_type = "pci";
|
|
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "sys", "pmc", "msi", "legacy", "err";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
|
+ <0 0 0 2 &pcie_intc 1>,
|
|
+ <0 0 0 3 &pcie_intc 2>,
|
|
+ <0 0 0 4 &pcie_intc 3>;
|
|
+ linux,pci-domain = <0>;
|
|
+ num-ib-windows = <6>;
|
|
+ num-ob-windows = <2>;
|
|
+ max-link-speed = <2>;
|
|
+ msi-map = <0x0 &gic 0x0 0x1000>;
|
|
+ num-lanes = <1>;
|
|
+ phys = <&combphy2_psq PHY_TYPE_PCIE>;
|
|
+ phy-names = "pcie-phy";
|
|
+ power-domains = <&power RK3568_PD_PIPE>;
|
|
+ reg = <0x3 0xc0000000 0x0 0x400000>,
|
|
+ <0x0 0xfe260000 0x0 0x10000>,
|
|
+ <0x3 0x3f800000 0x0 0x800000>;
|
|
+ ranges = <0x1000000 0x0 0x7f700000 0x3 0x3f700000 0x0 0x00100000
|
|
+ 0x2000000 0x0 0x40000000 0x3 0x00000000 0x0 0x3f700000>;
|
|
+ reg-names = "dbi", "apb", "config";
|
|
+ resets = <&cru SRST_PCIE20_POWERUP>;
|
|
+ reset-names = "pipe";
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie_intc: legacy-interrupt-controller {
|
|
+ #address-cells = <0>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-controller;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
|
|
+ };
|
|
+
|
|
+ };
|
|
+
|
|
+ sdmmc0: mmc@fe2b0000 {
|
|
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
|
|
+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
|
|
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
+ fifo-depth = <0x100>;
|
|
+ max-frequency = <150000000>;
|
|
+ resets = <&cru SRST_SDMMC0>;
|
|
+ reset-names = "reset";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdmmc1: mmc@fe2c0000 {
|
|
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
|
|
+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
|
|
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
+ fifo-depth = <0x100>;
|
|
+ max-frequency = <150000000>;
|
|
+ resets = <&cru SRST_SDMMC1>;
|
|
+ reset-names = "reset";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sfc: spi@fe300000 {
|
|
+ compatible = "rockchip,sfc";
|
|
+ reg = <0x0 0xfe300000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
|
+ clock-names = "clk_sfc", "hclk_sfc";
|
|
+ pinctrl-0 = <&fspi_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ sdhci: mmc@fe310000 {
|
|
+ compatible = "rockchip,rk3568-dwcmshc";
|
|
+ reg = <0x0 0xfe310000 0x0 0x10000>;
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
|
|
+ assigned-clock-rates = <200000000>, <24000000>;
|
|
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
|
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
|
+ <&cru TCLK_EMMC>;
|
|
+ clock-names = "core", "bus", "axi", "block", "timer";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spdif: spdif@fe460000 {
|
|
+ compatible = "rockchip,rk3568-spdif";
|
|
+ reg = <0x0 0xfe460000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clock-names = "mclk", "hclk";
|
|
+ clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
|
|
+ dmas = <&dmac1 1>;
|
|
+ dma-names = "tx";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spdifm0_tx>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s1_8ch: i2s@fe410000 {
|
|
+ compatible = "rockchip,rk3568-i2s-tdm";
|
|
+ reg = <0x0 0xfe410000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
|
|
+ assigned-clock-rates = <1188000000>, <1188000000>;
|
|
+ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
|
|
+ <&cru HCLK_I2S1_8CH>;
|
|
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
+ dmas = <&dmac1 3>, <&dmac1 2>;
|
|
+ dma-names = "rx", "tx";
|
|
+ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
|
|
+ reset-names = "tx-m", "rx-m";
|
|
+ rockchip,grf = <&grf>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
|
|
+ &i2s1m0_lrcktx &i2s1m0_lrckrx
|
|
+ &i2s1m0_sdi0 &i2s1m0_sdi1
|
|
+ &i2s1m0_sdi2 &i2s1m0_sdi3
|
|
+ &i2s1m0_sdo0 &i2s1m0_sdo1
|
|
+ &i2s1m0_sdo2 &i2s1m0_sdo3>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ dmac0: dmac@fe530000 {
|
|
+ compatible = "arm,pl330", "arm,primecell";
|
|
+ reg = <0x0 0xfe530000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ arm,pl330-periph-burst;
|
|
+ clocks = <&cru ACLK_BUS>;
|
|
+ clock-names = "apb_pclk";
|
|
+ #dma-cells = <1>;
|
|
+ };
|
|
+
|
|
+ dmac1: dmac@fe550000 {
|
|
+ compatible = "arm,pl330", "arm,primecell";
|
|
+ reg = <0x0 0xfe550000 0x0 0x4000>;
|
|
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ arm,pl330-periph-burst;
|
|
+ clocks = <&cru ACLK_BUS>;
|
|
+ clock-names = "apb_pclk";
|
|
+ #dma-cells = <1>;
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@fe5a0000 {
|
|
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5a0000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ pinctrl-0 = <&i2c1_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@fe5b0000 {
|
|
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5b0000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ pinctrl-0 = <&i2c2m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@fe5c0000 {
|
|
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5c0000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ pinctrl-0 = <&i2c3m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c4: i2c@fe5d0000 {
|
|
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5d0000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ pinctrl-0 = <&i2c4m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c5: i2c@fe5e0000 {
|
|
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
|
|
+ reg = <0x0 0xfe5e0000 0x0 0x1000>;
|
|
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
|
+ clock-names = "i2c", "pclk";
|
|
+ pinctrl-0 = <&i2c5m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ wdt: watchdog@fe600000 {
|
|
+ compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
|
|
+ reg = <0x0 0xfe600000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
|
+ clock-names = "tclk", "pclk";
|
|
+ };
|
|
+
|
|
+ uart1: serial@fe650000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe650000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 2>, <&dmac0 3>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart1m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart2: serial@fe660000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe660000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 4>, <&dmac0 5>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart2m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart3: serial@fe670000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe670000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 6>, <&dmac0 7>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart3m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart4: serial@fe680000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe680000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 8>, <&dmac0 9>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart4m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart5: serial@fe690000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe690000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 10>, <&dmac0 11>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart5m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart6: serial@fe6a0000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe6a0000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 12>, <&dmac0 13>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart6m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart7: serial@fe6b0000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe6b0000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 14>, <&dmac0 15>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart7m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart8: serial@fe6c0000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe6c0000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 16>, <&dmac0 17>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart8m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart9: serial@fe6d0000 {
|
|
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
|
+ reg = <0x0 0xfe6d0000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
|
+ clock-names = "baudclk", "apb_pclk";
|
|
+ dmas = <&dmac0 18>, <&dmac0 19>;
|
|
+ dma-names = "tx", "rx";
|
|
+ pinctrl-0 = <&uart9m0_xfer>;
|
|
+ pinctrl-names = "default";
|
|
+ reg-io-width = <4>;
|
|
+ reg-shift = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ thermal_zones: thermal-zones {
|
|
+ cpu_thermal: cpu-thermal {
|
|
+ polling-delay-passive = <100>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsadc 0>;
|
|
+
|
|
+ trips {
|
|
+ cpu_alert0: cpu_alert0 {
|
|
+ temperature = <70000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "passive";
|
|
+ };
|
|
+ cpu_alert1: cpu_alert1 {
|
|
+ temperature = <75000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "passive";
|
|
+ };
|
|
+ cpu_crit: cpu_crit {
|
|
+ temperature = <95000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cooling-maps {
|
|
+ map0 {
|
|
+ trip = <&cpu_alert0>;
|
|
+ cooling-device =
|
|
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gpu_thermal: gpu-thermal {
|
|
+ polling-delay-passive = <20>; /* milliseconds */
|
|
+ polling-delay = <1000>; /* milliseconds */
|
|
+
|
|
+ thermal-sensors = <&tsadc 1>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ tsadc: tsadc@fe710000 {
|
|
+ compatible = "rockchip,rk3568-tsadc";
|
|
+ reg = <0x0 0xfe710000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
|
|
+ assigned-clock-rates = <17000000>, <700000>;
|
|
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
|
+ clock-names = "tsadc", "apb_pclk";
|
|
+ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
|
|
+ <&cru SRST_TSADCPHY>;
|
|
+ rockchip,grf = <&grf>;
|
|
+ rockchip,hw-tshut-temp = <95000>;
|
|
+ pinctrl-names = "init", "default", "sleep";
|
|
+ pinctrl-0 = <&tsadc_pin>;
|
|
+ pinctrl-1 = <&tsadc_shutorg>;
|
|
+ pinctrl-2 = <&tsadc_pin>;
|
|
+ #thermal-sensor-cells = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ saradc: saradc@fe720000 {
|
|
+ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
|
|
+ reg = <0x0 0xfe720000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
|
+ clock-names = "saradc", "apb_pclk";
|
|
+ resets = <&cru SRST_P_SARADC>;
|
|
+ reset-names = "saradc-apb";
|
|
+ #io-channel-cells = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm4: pwm@fe6e0000 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6e0000 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm4_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm5: pwm@fe6e0010 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6e0010 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm5_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm6: pwm@fe6e0020 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6e0020 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm6_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm7: pwm@fe6e0030 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6e0030 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm7_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm8: pwm@fe6f0000 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6f0000 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm8m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm9: pwm@fe6f0010 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6f0010 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm9m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm10: pwm@fe6f0020 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6f0020 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm10m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm11: pwm@fe6f0030 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe6f0030 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm11m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm12: pwm@fe700000 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe700000 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm12m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm13: pwm@fe700010 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe700010 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm13m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm14: pwm@fe700020 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe700020 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm14m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pwm15: pwm@fe700030 {
|
|
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
|
+ reg = <0x0 0xfe700030 0x0 0x10>;
|
|
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
+ clock-names = "pwm", "pclk";
|
|
+ pinctrl-0 = <&pwm15m0_pins>;
|
|
+ pinctrl-names = "active";
|
|
+ #pwm-cells = <3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ combphy1_usq: phy@fe830000 {
|
|
+ compatible = "rockchip,rk3568-naneng-combphy";
|
|
+ reg = <0x0 0xfe830000 0x0 0x100>;
|
|
+ #phy-cells = <1>;
|
|
+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
|
|
+ assigned-clock-rates = <100000000>;
|
|
+ clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
|
|
+ <&cru PCLK_PIPE>;
|
|
+ clock-names = "ref", "apb", "pipe";
|
|
+ resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
|
|
+ reset-names = "combphy-apb", "combphy";
|
|
+ rockchip,pipe-grf = <&pipegrf>;
|
|
+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ combphy2_psq: phy@fe840000 {
|
|
+ compatible = "rockchip,rk3568-naneng-combphy";
|
|
+ reg = <0x0 0xfe840000 0x0 0x100>;
|
|
+ #phy-cells = <1>;
|
|
+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
|
|
+ assigned-clock-rates = <100000000>;
|
|
+ clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
|
|
+ <&cru PCLK_PIPE>;
|
|
+ clock-names = "ref", "apb", "pipe";
|
|
+ resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
|
|
+ reset-names = "combphy-apb", "combphy";
|
|
+ rockchip,pipe-grf = <&pipegrf>;
|
|
+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb2phy0: usb2-phy@fe8a0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy";
|
|
+ reg = <0x0 0xfe8a0000 0x0 0x10000>;
|
|
+ clocks = <&pmucru CLK_USBPHY0_REF>;
|
|
+ clock-names = "phyclk";
|
|
+ #clock-cells = <0>;
|
|
+ clock-output-names = "usb480m_phy";
|
|
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ rockchip,usbgrf = <&usb2phy0_grf>;
|
|
+ status = "disabled";
|
|
+
|
|
+ u2phy0_host: host-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ u2phy0_otg: otg-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2phy1: usb2-phy@fe8b0000 {
|
|
+ compatible = "rockchip,rk3568-usb2phy";
|
|
+ reg = <0x0 0xfe8b0000 0x0 0x10000>;
|
|
+ clocks = <&pmucru CLK_USBPHY1_REF>;
|
|
+ clock-names = "phyclk";
|
|
+ #clock-cells = <0>;
|
|
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ rockchip,usbgrf = <&usb2phy1_grf>;
|
|
+ status = "disabled";
|
|
+
|
|
+ u2phy1_host: host-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ u2phy1_otg: otg-port {
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pinctrl: pinctrl {
|
|
+ compatible = "rockchip,rk3568-pinctrl";
|
|
+ rockchip,grf = <&grf>;
|
|
+ rockchip,pmu = <&pmugrf>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+
|
|
+ gpio0: gpio@fdd60000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfdd60000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio1: gpio@fe740000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfe740000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio2: gpio@fe750000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfe750000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio3: gpio@fe760000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfe760000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio4: gpio@fe770000 {
|
|
+ compatible = "rockchip,gpio-bank";
|
|
+ reg = <0x0 0xfe770000 0x0 0x100>;
|
|
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+#include "rk3568-pinctrl.dtsi"
|
|
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
|
|
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
|
|
@@ -55,7 +55,7 @@ enum {
|
|
};
|
|
|
|
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
|
|
- [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
|
|
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000",
|
|
[BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
|
|
[BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
|
|
};
|