mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
200 lines
6.6 KiB
Diff
200 lines
6.6 KiB
Diff
From 440c62b5e741b22e004327b692a5f5003cc4f31b Mon Sep 17 00:00:00 2001
|
|
From: Maxime Ripard <maxime@cerno.tech>
|
|
Date: Mon, 21 Nov 2022 17:04:31 +0100
|
|
Subject: [PATCH] drm/vc4: tests: Fail the current test if we access a register
|
|
|
|
Accessing a register when running under kunit is a bad idea since our
|
|
device is completely mocked.
|
|
|
|
Fail the current test if we ever access any of our hardware registers.
|
|
|
|
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
|
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_crtc.c | 13 +++++++++++--
|
|
drivers/gpu/drm/vc4/vc4_dpi.c | 13 +++++++++++--
|
|
drivers/gpu/drm/vc4/vc4_drv.h | 29 +++++++++++++++++++++++++----
|
|
drivers/gpu/drm/vc4/vc4_dsi.c | 9 ++++++++-
|
|
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 4 ++++
|
|
drivers/gpu/drm/vc4/vc4_txp.c | 13 +++++++++++--
|
|
drivers/gpu/drm/vc4/vc4_vec.c | 13 +++++++++++--
|
|
7 files changed, 81 insertions(+), 13 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
|
|
@@ -50,8 +50,17 @@
|
|
|
|
#define HVS_FIFO_LATENCY_PIX 6
|
|
|
|
-#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
|
|
-#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
|
|
+#define CRTC_WRITE(offset, val) \
|
|
+ do { \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ writel(val, vc4_crtc->regs + (offset)); \
|
|
+ } while (0)
|
|
+
|
|
+#define CRTC_READ(offset) \
|
|
+ ({ \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ readl(vc4_crtc->regs + (offset)); \
|
|
+ })
|
|
|
|
static const struct debugfs_reg32 crtc_regs[] = {
|
|
VC4_REG32(PV_CONTROL),
|
|
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
|
|
@@ -103,8 +103,17 @@ to_vc4_dpi(struct drm_encoder *encoder)
|
|
return container_of(encoder, struct vc4_dpi, encoder.base);
|
|
}
|
|
|
|
-#define DPI_READ(offset) readl(dpi->regs + (offset))
|
|
-#define DPI_WRITE(offset, val) writel(val, dpi->regs + (offset))
|
|
+#define DPI_READ(offset) \
|
|
+ ({ \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ readl(dpi->regs + (offset)); \
|
|
+ })
|
|
+
|
|
+#define DPI_WRITE(offset, val) \
|
|
+ do { \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ writel(val, dpi->regs + (offset)); \
|
|
+ } while (0)
|
|
|
|
static const struct debugfs_reg32 dpi_regs[] = {
|
|
VC4_REG32(DPI_C),
|
|
--- a/drivers/gpu/drm/vc4/vc4_drv.h
|
|
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
|
|
@@ -19,6 +19,8 @@
|
|
#include <drm/drm_mm.h>
|
|
#include <drm/drm_modeset_lock.h>
|
|
|
|
+#include <kunit/test-bug.h>
|
|
+
|
|
#include "uapi/drm/vc4_drm.h"
|
|
#include "vc4_regs.h"
|
|
|
|
@@ -669,10 +671,29 @@ to_vc4_crtc_state(const struct drm_crtc_
|
|
return container_of(crtc_state, struct vc4_crtc_state, base);
|
|
}
|
|
|
|
-#define V3D_READ(offset) readl(vc4->v3d->regs + offset)
|
|
-#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
|
|
-#define HVS_READ(offset) readl(hvs->regs + offset)
|
|
-#define HVS_WRITE(offset, val) writel(val, hvs->regs + offset)
|
|
+#define V3D_READ(offset) \
|
|
+ ({ \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ readl(vc4->v3d->regs + (offset)); \
|
|
+ })
|
|
+
|
|
+#define V3D_WRITE(offset, val) \
|
|
+ do { \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ writel(val, vc4->v3d->regs + (offset)); \
|
|
+ } while (0)
|
|
+
|
|
+#define HVS_READ(offset) \
|
|
+ ({ \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ readl(hvs->regs + (offset)); \
|
|
+ })
|
|
+
|
|
+#define HVS_WRITE(offset, val) \
|
|
+ do { \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ writel(val, hvs->regs + (offset)); \
|
|
+ } while (0)
|
|
|
|
#define VC4_REG32(reg) { .name = #reg, .offset = reg }
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_dsi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
|
|
@@ -623,6 +623,8 @@ dsi_dma_workaround_write(struct vc4_dsi
|
|
dma_cookie_t cookie;
|
|
int ret;
|
|
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n");
|
|
+
|
|
/* DSI0 should be able to write normally. */
|
|
if (!chan) {
|
|
writel(val, dsi->regs + offset);
|
|
@@ -651,7 +653,12 @@ dsi_dma_workaround_write(struct vc4_dsi
|
|
DRM_ERROR("Failed to wait for DMA: %d\n", ret);
|
|
}
|
|
|
|
-#define DSI_READ(offset) readl(dsi->regs + (offset))
|
|
+#define DSI_READ(offset) \
|
|
+ ({ \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ readl(dsi->regs + (offset)); \
|
|
+ })
|
|
+
|
|
#define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
|
|
#define DSI_PORT_READ(offset) \
|
|
DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
|
|
--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
|
|
+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
|
|
@@ -456,6 +456,8 @@ static inline u32 vc4_hdmi_read(struct v
|
|
|
|
WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
|
|
|
|
+ kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
|
|
+
|
|
if (reg >= variant->num_registers) {
|
|
dev_warn(&hdmi->pdev->dev,
|
|
"Invalid register ID %u\n", reg);
|
|
@@ -486,6 +488,8 @@ static inline void vc4_hdmi_write(struct
|
|
|
|
WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
|
|
|
|
+ kunit_fail_current_test("Accessing an HDMI register in a unit test!\n");
|
|
+
|
|
if (reg >= variant->num_registers) {
|
|
dev_warn(&hdmi->pdev->dev,
|
|
"Invalid register ID %u\n", reg);
|
|
--- a/drivers/gpu/drm/vc4/vc4_txp.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_txp.c
|
|
@@ -145,8 +145,17 @@
|
|
/* Number of lines received and committed to memory. */
|
|
#define TXP_PROGRESS 0x10
|
|
|
|
-#define TXP_READ(offset) readl(txp->regs + (offset))
|
|
-#define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))
|
|
+#define TXP_READ(offset) \
|
|
+ ({ \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ readl(txp->regs + (offset)); \
|
|
+ })
|
|
+
|
|
+#define TXP_WRITE(offset, val) \
|
|
+ do { \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ writel(val, txp->regs + (offset)); \
|
|
+ } while (0)
|
|
|
|
struct vc4_txp {
|
|
struct vc4_crtc base;
|
|
--- a/drivers/gpu/drm/vc4/vc4_vec.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_vec.c
|
|
@@ -207,8 +207,17 @@ struct vc4_vec {
|
|
struct debugfs_regset32 regset;
|
|
};
|
|
|
|
-#define VEC_READ(offset) readl(vec->regs + (offset))
|
|
-#define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))
|
|
+#define VEC_READ(offset) \
|
|
+ ({ \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ readl(vec->regs + (offset)); \
|
|
+ })
|
|
+
|
|
+#define VEC_WRITE(offset, val) \
|
|
+ do { \
|
|
+ kunit_fail_current_test("Accessing a register in a unit test!\n"); \
|
|
+ writel(val, vec->regs + (offset)); \
|
|
+ } while (0)
|
|
|
|
static inline struct vc4_vec *
|
|
encoder_to_vc4_vec(struct drm_encoder *encoder)
|