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			76 lines
		
	
	
	
		
			2.6 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			76 lines
		
	
	
	
		
			2.6 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From 532e5242834ce05eef55cee19ba813f49f685b92 Mon Sep 17 00:00:00 2001
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| From: Phil Elwell <phil@raspberrypi.com>
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| Date: Fri, 4 Dec 2020 15:20:36 +0000
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| Subject: [PATCH] i2c: designware: Add SMBUS quick command support
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| 
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| The SMBUS emulation code turns an SMBUS quick command into a zero-
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| length read. This controller can't do zero length accesses, but it
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| can do quick commands, so reverse the emulation. The alternative
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| would be to properly implement the SMBUS support but that is a lot
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| more work, and unnecessary just to get i2cdetect working.
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| 
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| Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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| ---
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|  drivers/i2c/busses/i2c-designware-core.h   |  2 ++
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|  drivers/i2c/busses/i2c-designware-master.c | 17 +++++++++++++++--
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|  2 files changed, 17 insertions(+), 2 deletions(-)
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| 
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| --- a/drivers/i2c/busses/i2c-designware-core.h
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| +++ b/drivers/i2c/busses/i2c-designware-core.h
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| @@ -117,7 +117,9 @@
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|  
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|  #define DW_IC_ERR_TX_ABRT	0x1
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|  
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| +#define DW_IC_TAR_SPECIAL		BIT(11)
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|  #define DW_IC_TAR_10BITADDR_MASTER	BIT(12)
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| +#define DW_IC_TAR_SMBUS_QUICK_CMD	BIT(16)
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|  
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|  #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH	(BIT(2) | BIT(3))
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|  #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK	GENMASK(3, 2)
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| --- a/drivers/i2c/busses/i2c-designware-master.c
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| +++ b/drivers/i2c/busses/i2c-designware-master.c
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| @@ -228,6 +228,10 @@ static void i2c_dw_xfer_init(struct dw_i
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|  		ic_tar = DW_IC_TAR_10BITADDR_MASTER;
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|  	}
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|  
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| +	/* Convert a zero-length read into an SMBUS quick command */
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| +	if (!msgs[dev->msg_write_idx].len)
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| +		ic_tar = DW_IC_TAR_SPECIAL | DW_IC_TAR_SMBUS_QUICK_CMD;
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| +
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|  	regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
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|  			   ic_con);
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|  
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| @@ -409,6 +413,14 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
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|  		regmap_read(dev->map, DW_IC_RXFLR, &flr);
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|  		rx_limit = dev->rx_fifo_depth - flr;
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|  
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| +		/* Handle SMBUS quick commands */
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| +		if (!buf_len) {
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| +			if (msgs[dev->msg_write_idx].flags & I2C_M_RD)
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| +				regmap_write(dev->map, DW_IC_DATA_CMD, 0x300);
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| +			else
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| +				regmap_write(dev->map, DW_IC_DATA_CMD, 0x200);
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| +		}
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| +
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|  		while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
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|  			u32 cmd = 0;
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|  
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| @@ -660,7 +672,7 @@ static const struct i2c_algorithm i2c_dw
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|  };
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|  
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|  static const struct i2c_adapter_quirks i2c_dw_quirks = {
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| -	.flags = I2C_AQ_NO_ZERO_LEN,
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| +	.flags = 0,
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|  };
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|  
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|  static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
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| @@ -800,7 +812,8 @@ void i2c_dw_configure_master(struct dw_i
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|  {
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|  	struct i2c_timings *t = &dev->timings;
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|  
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| -	dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
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| +	dev->functionality = I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_QUICK |
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| +			     DW_IC_DEFAULT_FUNCTIONALITY;
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|  
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|  	dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
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|  			  DW_IC_CON_RESTART_EN;
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