mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Update rockchip support
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
c3f3d71345
commit
51e65a546f
22 changed files with 4960 additions and 61 deletions
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@ -104,17 +104,6 @@ define U-Boot/nanopi-r4se-rk3399
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USE_RKBIN:=1
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endef
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define U-Boot/nanopi-r5s-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=NanoPi R5S
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r5s
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DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.28.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/rock-pi-4-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=Rock Pi 4
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@ -146,6 +135,17 @@ define U-Boot/rongpin-king3399-rk3399
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USE_RKBIN:=1
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endef
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define U-Boot/rocktech-mpc1903-rk3399
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BUILD_SUBTARGET:=armv8
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NAME:=Rocktech MPC1903
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BUILD_DEVICES:= \
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rocktech_mpc1903
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DEPENDS:=+PACKAGE_u-boot-rocktech-mpc1903-rk3399:arm-trusted-firmware-rk3399
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3399_bl31_v1.35.elf
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USE_RKBIN:=1
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endef
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# RK3568 boards
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define U-Boot/mrkaio-m68s-rk3568
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@ -163,6 +163,7 @@ define U-Boot/opc-h68k-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=OPC-H68K Board
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BUILD_DEVICES:= \
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hinlink_opc-h66k \
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hinlink_opc-h68k
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DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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@ -170,6 +171,28 @@ define U-Boot/opc-h68k-rk3568
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/photonicat-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=Ariaboard Photonicat
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BUILD_DEVICES:= \
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ariaboard_photonicat
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DEPENDS:=+PACKAGE_u-boot-photonicat-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.28.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/radxa-e25-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=Radxa E25
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BUILD_DEVICES:= \
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radxa_e25
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DEPENDS:=+PACKAGE_u-boot-radxa-e25-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.28.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/rock-3a-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=ROCK3 Model A
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@ -181,17 +204,6 @@ define U-Boot/rock-3a-rk3568
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/rock-pi-e25-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=ROCK Pi E25
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BUILD_DEVICES:= \
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radxa_rock-pi-e25
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DEPENDS:=+PACKAGE_u-boot-rock-pi-e25-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.28.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/r66s-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=R66S/R68S
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@ -215,20 +227,45 @@ define U-Boot/station-p2-rk3568
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/nanopi-r5s-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=NanoPi R5S
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r5s
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DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.28.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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define U-Boot/nanopi-r5c-rk3568
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BUILD_SUBTARGET:=armv8
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NAME:=NanoPi R5C
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BUILD_DEVICES:= \
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friendlyarm_nanopi-r5c
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DEPENDS:=+PACKAGE_u-boot-nanopi-r5c-rk3568:arm-trusted-firmware-rk3568
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PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
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ATF:=rk3568_bl31_v1.28.elf
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DDR:=rk3568_ddr_1560MHz_v1.13.bin
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endef
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UBOOT_TARGETS := \
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mrkaio-m68s-rk3568 \
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opc-h68k-rk3568 \
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photonicat-rk3568 \
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radxa-e25-rk3568 \
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rock-3a-rk3568 \
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rock-pi-e25-rk3568 \
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r66s-rk3568 \
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station-p2-rk3568 \
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guangmiao-g4c-rk3399 \
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nanopi-r4s-rk3399 \
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nanopi-r4se-rk3399 \
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nanopi-r5s-rk3568 \
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nanopi-r5c-rk3568 \
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rock-pi-4-rk3399 \
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rockpro64-rk3399 \
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rongpin-king3399-rk3399 \
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rocktech-mpc1903-rk3399 \
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nanopi-r2c-rk3328 \
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nanopi-r2s-rk3328 \
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orangepi-r1-plus-rk3328 \
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@ -0,0 +1,42 @@
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From c9a8a3b5fb4ae210c5a5acb1538b0e961c5d1421 Mon Sep 17 00:00:00 2001
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From: Tang Yun ping <typ@rock-chips.com>
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Date: Wed, 23 Jun 2021 19:48:59 +0800
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Subject: [PATCH] rk356x: ddr: fix dbw detect bug
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Signed-off-by: Tang Yun ping <typ@rock-chips.com>
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Change-Id: Ifadad00853eb0ad43a68f12335fd243e6a1bc04b
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---
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drivers/ram/rockchip/sdram_common.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/ram/rockchip/sdram_common.c
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+++ b/drivers/ram/rockchip/sdram_common.c
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@@ -299,22 +299,22 @@ int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type)
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bw = cap_info->bw;
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cs_cap = (1 << (row + col + bk + bw - 20));
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if (bw == 2) {
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- if (cs_cap <= 0x2000000) /* 256Mb */
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+ if (cs_cap <= 0x20) /* 256Mb */
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die_bw_0 = (col < 9) ? 2 : 1;
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- else if (cs_cap <= 0x10000000) /* 2Gb */
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+ else if (cs_cap <= 0x100) /* 2Gb */
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die_bw_0 = (col < 10) ? 2 : 1;
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- else if (cs_cap <= 0x40000000) /* 8Gb */
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+ else if (cs_cap <= 0x400) /* 8Gb */
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die_bw_0 = (col < 11) ? 2 : 1;
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else
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die_bw_0 = (col < 12) ? 2 : 1;
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if (cs > 1) {
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row = cap_info->cs1_row;
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cs_cap = (1 << (row + col + bk + bw - 20));
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- if (cs_cap <= 0x2000000) /* 256Mb */
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+ if (cs_cap <= 0x20) /* 256Mb */
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die_bw_0 = (col < 9) ? 2 : 1;
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- else if (cs_cap <= 0x10000000) /* 2Gb */
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+ else if (cs_cap <= 0x100) /* 2Gb */
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die_bw_0 = (col < 10) ? 2 : 1;
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- else if (cs_cap <= 0x40000000) /* 8Gb */
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+ else if (cs_cap <= 0x400) /* 8Gb */
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die_bw_0 = (col < 11) ? 2 : 1;
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else
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die_bw_0 = (col < 12) ? 2 : 1;
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@ -0,0 +1,44 @@
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From c7496009386dbac8f8d18a94258031f30683d7c6 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 20 Feb 2022 07:59:02 -0500
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Subject: [PATCH] gpio: rockchip: fix building for spl
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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drivers/gpio/rk_gpio.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/common/spl/Kconfig
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+++ b/common/spl/Kconfig
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@@ -454,6 +454,11 @@ config SPL_FIT_IMAGE_TINY
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ensure this information is available to the next image
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invoked).
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+config SPL_ADC
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+ bool "Support ADC drivers in SPL"
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+ help
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+ Enable ADC drivers in SPL.
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+
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config SPL_CACHE
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bool "Support CACHE drivers"
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help
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--- a/drivers/Makefile
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+++ b/drivers/Makefile
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@@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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+obj-$(CONFIG_$(SPL_)ADC) += adc/
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obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
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obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
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obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/
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--- a/drivers/gpio/rk_gpio.c
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+++ b/drivers/gpio/rk_gpio.c
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@@ -118,7 +118,7 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
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}
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/* Simple SPL interface to GPIOs */
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-#ifdef CONFIG_SPL_BUILD
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+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ROCKCHIP_GPIO_V2)
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enum {
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PULL_NONE_1V8 = 0,
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@ -0,0 +1,28 @@
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From 5011ceb0da47f7c3d54d20b45b7df884e6e92ac5 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 20 Feb 2022 07:58:38 -0500
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Subject: [PATCH] clk: rockchip: rk3568: fix reset handler
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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drivers/clk/rockchip/clk_rk3568.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/clk/rockchip/clk_rk3568.c
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+++ b/drivers/clk/rockchip/clk_rk3568.c
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@@ -14,6 +14,7 @@
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/io.h>
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+#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3568-cru.h>
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@@ -2934,6 +2935,7 @@ static int rk3568_clk_bind(struct udevice *dev)
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glb_srst_fst);
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priv->glb_srst_snd_value = offsetof(struct rk3568_cru,
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glb_srsr_snd);
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+ dev_set_priv(sys_child, priv);
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}
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#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
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@ -0,0 +1,144 @@
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From 79cb33b9da0c9475486ca0759341057854b25e38 Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 20 Feb 2022 07:57:50 -0500
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Subject: [PATCH] rockchip: handle bootrom mode in spl
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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---
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arch/arm/mach-rockchip/Makefile | 6 +--
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arch/arm/mach-rockchip/boot_mode.c | 4 +-
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arch/arm/mach-rockchip/rk3568/rk3568.c | 54 +++++++++++++++++++++++++-
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3 files changed, 59 insertions(+), 5 deletions(-)
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--- a/arch/arm/mach-rockchip/Makefile
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+++ b/arch/arm/mach-rockchip/Makefile
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@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
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obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
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-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
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-
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# Always include boot_mode.o, as we bypass it (i.e. turn it off)
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# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way,
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# we can have the preprocessor correctly recognise both 0x0 and 0
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# meaning "turn it off".
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-obj-y += boot_mode.o
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+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o
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+
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+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
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obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
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obj-$(CONFIG_MISC_INIT_R) += misc.o
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endif
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--- a/arch/arm/mach-rockchip/boot_mode.c
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+++ b/arch/arm/mach-rockchip/boot_mode.c
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@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void)
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ret = -ENODEV;
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uclass_foreach_dev(dev, uc) {
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if (!strncmp(dev->name, "saradc", 6)) {
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- ret = adc_channel_single_shot(dev->name, 1, &val);
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+ ret = adc_channel_single_shot(dev->name, 0, &val);
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break;
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}
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}
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@@ -89,6 +89,7 @@ int setup_boot_mode(void)
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boot_mode = readl(reg);
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debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
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+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
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/* Clear boot mode */
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writel(BOOT_NORMAL, reg);
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@@ -102,6 +103,7 @@ int setup_boot_mode(void)
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env_set("preboot", "setenv preboot; ums mmc 0");
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break;
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}
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+#endif
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return 0;
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}
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--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
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+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
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@@ -9,19 +9,30 @@
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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+#include <asm/arch-rockchip/boot_mode.h>
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#include <asm/arch-rockchip/grf_rk3568.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <dt-bindings/clock/rk3568-cru.h>
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#define PMUGRF_BASE 0xfdc20000
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#define GRF_BASE 0xfdc60000
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+#define GRF_GPIO1B_IOMUX_H 0x0c
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+#define GRF_GPIO1C_IOMUX_L 0x10
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+#define GRF_GPIO1C_IOMUX_H 0x14
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+#define GRF_GPIO1D_IOMUX_L 0x18
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+#define GRF_GPIO1D_IOMUX_H 0x1c
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+#define GRF_GPIO2A_IOMUX_L 0x20
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#define GRF_GPIO1B_DS_2 0x218
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#define GRF_GPIO1B_DS_3 0x21c
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#define GRF_GPIO1C_DS_0 0x220
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#define GRF_GPIO1C_DS_1 0x224
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#define GRF_GPIO1C_DS_2 0x228
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#define GRF_GPIO1C_DS_3 0x22c
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-#define SGRF_BASE 0xFDD18000
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+#define GRF_GPIO1D_DS_0 0x230
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+#define GRF_GPIO1D_DS_1 0x234
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+#define GRF_GPIO1D_DS_2 0x238
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+#define SGRF_BASE 0xfdd18000
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+#define SGRF_SOC_CON3 0x0c
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#define SGRF_SOC_CON4 0x10
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#define EMMC_HPROT_SECURE_CTRL 0x03
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#define SDMMC0_HPROT_SECURE_CTRL 0x01
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@@ -133,6 +144,24 @@ int arch_cpu_init(void)
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
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+
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+ /* emmc, sfc, and sdmmc iomux */
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
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+ writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_H);
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+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO2A_IOMUX_L);
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+
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+ /* set the fspi d0~3 cs0 to level 2 */
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+ writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3);
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+ writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0);
|
||||
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1);
|
||||
+ writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2);
|
||||
+
|
||||
+ /* Set the fspi to secure */
|
||||
+ writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
|
||||
+
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
@@ -164,3 +193,26 @@ int ft_system_setup(void *blob, struct bd_info *bd)
|
||||
return 0;
|
||||
};
|
||||
#endif
|
||||
+
|
||||
+#ifdef CONFIG_SPL_BUILD
|
||||
+
|
||||
+void __weak led_setup(void)
|
||||
+{
|
||||
+}
|
||||
+
|
||||
+void spl_board_init(void)
|
||||
+{
|
||||
+ led_setup();
|
||||
+
|
||||
+#if defined(SPL_DM_REGULATOR)
|
||||
+ /*
|
||||
+ * Turning the eMMC and SPI back on (if disabled via the Qseven
|
||||
+ * BIOS_ENABLE) signal is done through a always-on regulator).
|
||||
+ */
|
||||
+ if (regulators_enable_boot_on(false))
|
||||
+ debug("%s: Cannot enable boot on regulator\n", __func__);
|
||||
+#endif
|
||||
+
|
||||
+ setup_boot_mode();
|
||||
+}
|
||||
+#endif
|
||||
|
|
@ -0,0 +1,784 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -165,6 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
|
||||
rk3399-rock-pi-4b.dtb \
|
||||
rk3399-rock-pi-4c.dtb \
|
||||
rk3399-rock960.dtb \
|
||||
+ rk3399-mpc1903.dtb \
|
||||
rk3399-rockpro64.dtb \
|
||||
rk3399pro-rock-pi-n10.dtb
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-mpc1903.dts
|
||||
@@ -0,0 +1,688 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/input/linux-event-codes.h>
|
||||
+#include "rk3399.dtsi"
|
||||
+#include "rk3399-opp.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Rocktech MPC1903";
|
||||
+ compatible = "rocktech,mpc1903", "rockchip,rk3399";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ clkin_gmac: external-gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "clkin_gmac";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vcc12v_dcin: dc-12v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc12v_dcin";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <12000000>;
|
||||
+ regulator-max-microvolt = <12000000>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk808 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable_h>;
|
||||
+ reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc12v_dcin>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_host: vcc5v0-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_host_en>;
|
||||
+ regulator-name = "vcc5v0_host";
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_lan: vcc-phy-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_lan";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_log: vdd-log {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm2 0 25000 1>;
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1400000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&status_led_pin>;
|
||||
+
|
||||
+ status_led: led-status-led {
|
||||
+ label = "status_led";
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hub_control {
|
||||
+ compatible = "rocktech,hub-control";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hub_pwr>;
|
||||
+ hub-pwr-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_l0 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l1 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l2 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_l3 {
|
||||
+ cpu-supply = <&vdd_cpu_l>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b0 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&cpu_b1 {
|
||||
+ cpu-supply = <&vdd_cpu_b>;
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
+ assigned-clock-parents = <&clkin_gmac>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-supply = <&vcc_lan>;
|
||||
+ phy-mode = "rmgii";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rgmii_pins>;
|
||||
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ snps,reset-delays-us = <0 10000 50000>;
|
||||
+ tx_delay = <0x28>;
|
||||
+ rx_delay = <0x11>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ ddc-i2c-bus = <&i2c3>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmi_i2c_xfer>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ clock-frequency = <400000>;
|
||||
+ i2c-scl-rising-time-ns = <168>;
|
||||
+ i2c-scl-falling-time-ns = <4>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk808: pmic@1b {
|
||||
+ compatible = "rockchip,rk808";
|
||||
+ reg = <0x1b>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk808-clkout2";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc5v0_sys>;
|
||||
+ vcc2-supply = <&vcc5v0_sys>;
|
||||
+ vcc3-supply = <&vcc5v0_sys>;
|
||||
+ vcc4-supply = <&vcc5v0_sys>;
|
||||
+ vcc6-supply = <&vcc5v0_sys>;
|
||||
+ vcc7-supply = <&vcc5v0_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc5v0_sys>;
|
||||
+ vcc10-supply = <&vcc5v0_sys>;
|
||||
+ vcc11-supply = <&vcc5v0_sys>;
|
||||
+ vcc12-supply = <&vcc3v3_sys>;
|
||||
+ vddio-supply = <&vcc_3v0>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_center: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_center";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_l: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_cpu_l";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gen_1v8: LDO_REG1 {
|
||||
+ regulator-name = "gen_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gen_3v0: LDO_REG2 {
|
||||
+ regulator-name = "gen_3v0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vcc1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sdio: LDO_REG4 {
|
||||
+ regulator-name = "vcc_sdio";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca3v0_codec: LDO_REG5 {
|
||||
+ regulator-name = "vcca3v0_codec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v5: LDO_REG6 {
|
||||
+ regulator-name = "vcc_1v5";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1500000>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_codec: LDO_REG7 {
|
||||
+ regulator-name = "vcc1v8_codec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v0: LDO_REG8 {
|
||||
+ regulator-name = "vcc_3v0";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3000000>;
|
||||
+ regulator-max-microvolt = <3000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s3: SWITCH_REG1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc3v3_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_s0: SWITCH_REG2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vcc3v3_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_cpu_b: regulator@40 {
|
||||
+ compatible = "silergy,syr827";
|
||||
+ reg = <0x40>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vsel1_pin>;
|
||||
+ regulator-name = "vdd_cpu_b";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: regulator@41 {
|
||||
+ compatible = "silergy,syr828";
|
||||
+ reg = <0x41>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vsel2_pin>;
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
+ regulator-ramp-delay = <1000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rtc: pcf85263@51 {
|
||||
+ compatible = "nxp,pcf85263";
|
||||
+ reg = <0x51>;
|
||||
+ pinctrl-0 = <&rtc_int>;
|
||||
+ rtc_int_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ i2c-scl-rising-time-ns = <300>;
|
||||
+ i2c-scl-falling-time-ns = <15>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ i2c-scl-rising-time-ns = <600>;
|
||||
+ i2c-scl-falling-time-ns = <20>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c6 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s0 {
|
||||
+ rockchip,i2s-broken-burst-len;
|
||||
+ rockchip,playback-channels = <8>;
|
||||
+ rockchip,capture-channels = <8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s2 {
|
||||
+ rockchip,bclk-fs = <128>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ bt656-supply = <&vcc_3v0>;
|
||||
+ audio-supply = <&vcc1v8_codec>;
|
||||
+ sdmmc-supply = <&vcc_sdio>;
|
||||
+ gpio1830-supply = <&vcc_3v0>;
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ pmu1830-supply = <&vcc_3v0>;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ bt {
|
||||
+ uart0_gpios: uart0-gpios {
|
||||
+ rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ vsel1_pin: vsel1-pin {
|
||||
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ vsel2_pin: vsel2-pin {
|
||||
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb2 {
|
||||
+ vcc5v0_host_en: vcc5v0-host-en {
|
||||
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ hub_pwr: hub-pwr {
|
||||
+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wifi {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rtc {
|
||||
+ rtc_int: rtc-int {
|
||||
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ led {
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ power_key: power-key {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ status = "okay";
|
||||
+ vref-supply = <&vcc_1v8>;
|
||||
+};
|
||||
+
|
||||
+&sdio0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ bus-width = <4>;
|
||||
+ clock-frequency = <50000000>;
|
||||
+ cap-sdio-irq;
|
||||
+ cap-sd-highspeed;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ clock-freq-min-max = <400000 150000000>;
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ supports-sd;
|
||||
+ disable-wp;
|
||||
+ num-slots = <1>;
|
||||
+ vqmmc-supply = <&vcc_sdio>;
|
||||
+ max-frequency = <150000000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-hs400-1_8v;
|
||||
+ mmc-hs400-enhanced-strobe;
|
||||
+ non-removable;
|
||||
+ supports-emmc;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tcphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+ rockchip,hw-tshut-temp = <120000>;
|
||||
+ /* tshut mode 0:CRU 1:GPIO */
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ /* tshut polarity 0:LOW 1:HIGH */
|
||||
+ rockchip,hw-tshut-polarity = <1>;
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+
|
||||
+&u2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3_1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_1 {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&vopb {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopb_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vopl_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3399-mpc1903-u-boot.dtsi
|
||||
@@ -0,0 +1,14 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+
|
||||
+#include "rk3399-u-boot.dtsi"
|
||||
+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/rocktech-mpc1903-rk3399_defconfig
|
||||
@@ -0,0 +1,63 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3399=y
|
||||
+CONFIG_TARGET_EVB_RK3399=y
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-mpc1903.dtb"
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
+CONFIG_TPL=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-mpc1903"
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_DM_VIDEO=y
|
||||
+CONFIG_DISPLAY=y
|
||||
+CONFIG_VIDEO_ROCKCHIP=y
|
||||
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
|
|
@ -1,17 +1,17 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -174,7 +174,8 @@ rk3568-evb.dtb \
|
||||
@@ -177,7 +177,8 @@ rk3568-evb.dtb \
|
||||
rk3568-mrkaio-m68s.dtb \
|
||||
rk3568-nanopi-r5s.dtb \
|
||||
rk3566-quartz64-a.dtb \
|
||||
- rk3568-rock-3a.dtb
|
||||
+ rk3568-rock-3a.dtb \
|
||||
+ rk3568-rock-pi-e25.dtb
|
||||
+ rk3568-radxa-e25.dtb
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
|
||||
rv1108-elgin-r1.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-rock-pi-e25-u-boot.dtsi
|
||||
+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi
|
||||
@@ -0,0 +1,21 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
|
|
@ -35,19 +35,24 @@
|
|||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-rock-pi-e25.dts
|
||||
@@ -0,0 +1,8 @@
|
||||
+++ b/arch/arm/dts/rk3568-radxa-e25.dts
|
||||
@@ -0,0 +1,13 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk3568-evb.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa ROCK Pi E25";
|
||||
+ compatible = "radxa,rockpi-e25", "rockchip,rk3568";
|
||||
+ model = "Radxa E25";
|
||||
+ compatible = "radxa,e25", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/configs/rock-pi-e25-rk3568_defconfig
|
||||
@@ -0,0 +1,98 @@
|
||||
+++ b/configs/radxa-e25-rk3568_defconfig
|
||||
@@ -0,0 +1,99 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
|
|
@ -55,7 +60,7 @@
|
|||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-pi-e25"
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
|
|
@ -72,7 +77,7 @@
|
|||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-pi-e25.dtb"
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
|
|
@ -80,8 +85,10 @@
|
|||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ADC=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
|
||||
+CONFIG_SPL_BOARD_INIT=y
|
||||
+CONFIG_CMD_ADC=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
|
|
@ -129,7 +136,6 @@
|
|||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_SYSRESET_PSCI=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -179,7 +179,8 @@
|
||||
rk3568-photonicat.dtb \
|
||||
rk3566-quartz64-a.dtb \
|
||||
rk3568-rock-3a.dtb \
|
||||
- rk3568-radxa-e25.dtb
|
||||
+ rk3568-radxa-e25.dtb \
|
||||
+ rk3568-nanopi-r5c.dtb
|
||||
|
||||
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
|
||||
rv1108-elgin-r1.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts
|
||||
@@ -0,0 +1,9 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3568-evb.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R5C";
|
||||
+ compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
|
||||
@@ -0,0 +1,25 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
|
||||
+ */
|
||||
+
|
||||
+#include "rk3568-u-boot.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ stdout-path = &uart2;
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ u-boot,dm-spl;
|
||||
+ u-boot,spl-fifo-mode;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ clock-frequency = <24000000>;
|
||||
+ u-boot,dm-spl;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
|
||||
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
|
||||
@@ -18,6 +18,11 @@
|
||||
help
|
||||
NanoPi R5S FriendlyElec is a board for Rockchp RK3568.
|
||||
|
||||
+config TARGET_NANOPI_R5C_RK3568
|
||||
+ bool "NanoPi R5C board"
|
||||
+ help
|
||||
+ NanoPi R5C FriendlyElec is a board for Rockchp RK3568.
|
||||
+
|
||||
config TARGET_QUARTZ64_A_RK3566
|
||||
bool "Quartz64 Model A RK3566 development board"
|
||||
help
|
||||
@@ -40,6 +45,7 @@
|
||||
source "board/rockchip/bpi-r2-pro-rk3568/Kconfig"
|
||||
source "board/rockchip/evb_rk3568/Kconfig"
|
||||
source "board/friendlyelec/nanopi-r5s-rk3568/Kconfig"
|
||||
+source "board/friendlyelec/nanopi-r5c-rk3568/Kconfig"
|
||||
source "board/pine64/quartz64-a-rk3566/Kconfig"
|
||||
|
||||
endif
|
||||
--- /dev/null
|
||||
+++ b/board/friendlyelec/nanopi-r5c-rk3568/Kconfig
|
||||
@@ -0,0 +1,15 @@
|
||||
+if TARGET_NANOPI_R5C_RK3568
|
||||
+
|
||||
+config SYS_BOARD
|
||||
+ default "nanopi-r5c-rk3568"
|
||||
+
|
||||
+config SYS_VENDOR
|
||||
+ default "friendlyelec"
|
||||
+
|
||||
+config SYS_CONFIG_NAME
|
||||
+ default "nanopi-r5c-rk3568"
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
+ def_bool y
|
||||
+
|
||||
+endif
|
||||
--- /dev/null
|
||||
+++ b/board/friendlyelec/nanopi-r5c-rk3568/Makefile
|
||||
@@ -0,0 +1,4 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0+
|
||||
+#
|
||||
+
|
||||
+obj-y += nanopi-r5c-rk3568.o
|
||||
--- /dev/null
|
||||
+++ b/board/friendlyelec/nanopi-r5c-rk3568/nanopi-r5c-rk3568.c
|
||||
@@ -0,0 +1,4 @@
|
||||
+ // SPDX-License-Identifier: GPL-2.0+
|
||||
+/*
|
||||
+ *
|
||||
+ */
|
||||
--- /dev/null
|
||||
+++ b/configs/nanopi-r5c-rk3568_defconfig
|
||||
@@ -0,0 +1,98 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00a00000
|
||||
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_NR_DRAM_BANKS=2
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_SPL_MMC=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_TARGET_NANOPI_R5C_RK3568=y
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2
|
||||
+CONFIG_API=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_OF_SYSTEM_SETUP=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
|
||||
+# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_SEPARATE_BSS=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
|
||||
+CONFIG_CMD_BIND=y
|
||||
+CONFIG_CMD_CLK=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_SPL_DM_WARN=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_ROCKCHIP_GPIO_V2=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_POWER_DOMAIN=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_DM_REGULATOR_GPIO=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_SYSRESET_PSCI=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_ROCKCHIP_USB2_PHY=y
|
||||
+CONFIG_USB_KEYBOARD=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
--- /dev/null
|
||||
+++ b/include/configs/nanopi-r5c-rk3568.h
|
||||
@@ -0,0 +1,14 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+
|
||||
+#ifndef __NANOPI_R5C_RK3568_H
|
||||
+#define __NANOPI_R5C_RK3568_H
|
||||
+
|
||||
+#include <configs/rk3568_common.h>
|
||||
+
|
||||
+#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
+
|
||||
+#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
+ "stdout=serial,vidconsole\0" \
|
||||
+ "stderr=serial,vidconsole\0"
|
||||
+
|
||||
+#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue